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Design Languages >> Verilog-AMS >> wrapping long instantiation lines
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Message started by makelo on May 22nd, 2007, 2:33pm

Title: wrapping long instantiation lines
Post by makelo on May 22nd, 2007, 2:33pm

Hello, I checked the LRM but could not find an answer.  Is there a way to break up long instantiation lines to help make them more readable and thereby avoid mistakes?  Something like the matlab command "..."

Here is an example section of code.

  GmCell_N1 #(.Ibias(Ibias),.Gmdiff(Gmdiff),.Rload(Rload)) BUT_R1C1(mida_p1s0,mida_p3s0,mida_p2s0,mida_p4s0,mida_p1s4,mida_p3s4,mida_p2s4,mida_p4s4,midb_p1s0,midb_p3s0,midb_p2s0,midb_p4s0,midb_p1s4,midb_p3s4,midb_p2s4,midb_p4s4);
  GmCell_N1 #(.Ibias(Ibias),.Gmdiff(Gmdiff),.Rload(Rload)) BUT_R2C1(mida_p1s2,mida_p3s2,mida_p2s2,mida_p4s2,mida_p1s6,mida_p3s6,mida_p2s6,mida_p4s6,midb_p1s2,midb_p3s2,midb_p2s2,midb_p4s2,midb_p1s6,midb_p3s6,midb_p2s6,midb_p4s6);
  GmCell_N1 #(.Ibias(Ibias),.Gmdiff(Gmdiff),.Rload(Rload)) BUT_R3C1(mida_p1s1,mida_p3s1,mida_p2s1,mida_p4s1,mida_p1s5,mida_p3s5,mida_p2s5,mida_p4s5,midb_p1s1,midb_p3s1,midb_p2s1,midb_p4s1,midb_p1s5,midb_p3s5,midb_p2s5,midb_p4s5);
  GmCell_N1 #(.Ibias(Ibias),.Gmdiff(Gmdiff),.Rload(Rload)) BUT_R4C1(mida_p1s3,mida_p3s3,mida_p2s3,mida_p4s3,mida_p1s7,mida_p3s7,mida_p2s7,mida_p4s7,midb_p1s3,midb_p3s3,midb_p2s3,midb_p4s3,midb_p1s7,midb_p3s7,midb_p2s7,midb_p4s7);

Title: Re: wrapping long instantiation lines
Post by Geoffrey_Coram on May 23rd, 2007, 4:43am

I believe any place you put a space you can put any amount of whitespace, including newlines.  

This should be OK:

GmCell_N1
 #(.Ibias(Ibias),.Gmdiff(Gmdiff),.Rload(Rload))
 BUT_R1C1(mida_p1s0,mida_p3s0,mida_p2s0,mida_p4s0,mida_p1s4,mida_p3s4,
        mida_p2s4,mida_p4s4,midb_p1s0,midb_p3s0,midb_p2s0,midb_p4s0,
       midb_p1s4,midb_p3s4,midb_p2s4,midb_p4s4);

Title: Re: wrapping long instantiation lines
Post by makelo on May 23rd, 2007, 7:22am

Thanks!  Yes this works.  The spaces are ignored so that I can put name and parameters which vary in length on one line and then arrange the pins on their own lines.  For modules with dozens of IO pins this is useful.

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