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Design >> RF Design >> Sources of Jitter
https://designers-guide.org/forum/YaBB.pl?num=1180002051

Message started by savithru on May 24^th, 2007, 3:20am

Title: Sources of Jitter
Post by savithru on May 24^th, 2007, 3:20am

hi

I am working on optimizing the PLL For better jitterperformance.

Now the earliar simulated jitter values are well with in the boundary. How ever the measured (post silicon) jitter values are outside the required boundary.

Can any of you plsease tell me how I can tackle the "Schematic" to reduce the Jitter.
i am starting with VCO ( Current Starved).

Pls tell what might have went wrong here.

Also kindly tell me the procedure to measuer the periodic Jitter and Long term Jitter.

Title: Re: Sources of Jitter
Post by adesign on May 28^th, 2007, 2:30am

Power supply noise contribute in remarkable jitter component.
See the PSRR of V-to-I converter in VCO.

Title: Re: Sources of Jitter
Post by adesign on Jun 8^th, 2007, 4:46am

For jitter measurement on Silicon, you can use wavecrest jitter measuring instruments.