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Design >> Analog Design >> Problem of settling time in SH
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Message started by Daniel H on May 25^th, 2007, 7:49pm

Title: Problem of settling time in SH
Post by Daniel H on May 25^th, 2007, 7:49pm

Hi,all
I designed a sample-and-hold circuit. When the design of opamp was finished, i used ideal switch and the opamp to make sample-and-hold. The performance of it can reach my spec: 8ns to 0.01%. But when i replaced ideal switch with bootstrapped switch, the output of S/H appeared large overshoot and the settling time was rised. I was puzzling! What happen to the S/H? Thanks
PS: The S/H is flip-around architecture :)
Daniel_H

Title: Re: Problem of settling time in SH
Post by aamar on May 29^th, 2007, 1:51am

Hi ,
As you said, you are using the bootstrap switch instead of the ideal switch, the main difference will be in the feedthrough effect which comes from the bootstrap capacitance, this means that the signal path will not be carrying only the signal to be sampled but also a part from the sampling clock signal, and the Opamp will sense both instead of one. This causes the overshoot and the longer settling time.

To avoid this, I think you have to optimize your bootstrap switch to reduce the capacitances, and to use dummy transistor to absorb this feed through signal or at least to reduce its effect, but in this case you need NOT(CLK) signal and increasing the BW of the amplifier will be helpful in any case.

Best regards,

aamar