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Modeling >> Behavioral Models >> Ver AMS Diff Amp Model (esp for HS CML logic gate)
https://designers-guide.org/forum/YaBB.pl?num=1180538195

Message started by jhjones on May 30^th, 2007, 8:16am

Title: Ver AMS Diff Amp Model (esp for HS CML logic gate)
Post by jhjones on May 30^th, 2007, 8:16am

Do you know if there is already a thread for Verilog AMS Differential Amplifier behavioral modeling (especially for High-Speed CML logic gates)? I'm looking to write a set of such models (my previous CML behavioral models were purely Verilog-D) -- maybe with a compile-time switch between Verilog-D and Verilog-AMS.

Title: Re: Ver AMS Diff Amp Model (esp for HS CML logic g
Post by jhjones on May 30^th, 2007, 10:50am

Found: http://www.bmas-conf.org/2006/4.1_paper.pdf

"Verification of CML circuits used in PLL contexts with Verilog-AMS"
Jonathan David
Scintera Networks, Inc.

Title: Re: Ver AMS Diff Amp Model (esp for HS CML logic g
Post by jhjones on May 30^th, 2007, 10:54am

http://www.designers-guide.org/Forum/YaBB.pl?num=1148909190 (Earlier thread about CML modeling ... not conclusive)

Title: Re: Ver AMS Diff Amp Model (esp for HS CML logic g
Post by jhjones on May 30^th, 2007, 11:32am

http://www.designers-guide.org/Forum/YaBB.pl?num=1164292846 (Note on Passive Element Modeling in a CML Context ... but inconclusive)