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Design Languages >> Verilog-AMS >> deep probe
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Message started by Venkateshr on May 31^st, 2007, 3:17am

Title: deep probe
Post by Venkateshr on May 31^st, 2007, 3:17am

how to probe a net which is deep inside the circuit ? I dont want to bring that to top level.All I can give is the full net name then my verilog-a block should make that available in top level.

this is similar to deepprobe block

Title: Re: deep probe
Post by rajdeep on May 31^st, 2007, 10:12am

I think try to use hierarchical names. To probe a net n1 which is in module A, and module A is in module Top use
Top.A.n1

Rajdeep

Title: Re: deep probe
Post by Venkateshr on May 31^st, 2007, 8:48pm

hierarchial addressing is ok but whether that net is accessible in the top level. I don't know

Title: Re: deep probe
Post by Geoffrey_Coram on Jun 1^st, 2007, 8:09am

I thought that you could always access something if you had its full hierarchical name.

Title: Re: deep probe
Post by Venkateshr on Jun 1^st, 2007, 10:07pm

thank you. I will try that.