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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Physical Verification, Extraction and Analysis >> Cascode LVS seems to match but.. https://designers-guide.org/forum/YaBB.pl?num=1180992455 Message started by .matteo on Jun 4th, 2007, 2:27pm |
Title: Cascode LVS seems to match but.. Post by .matteo on Jun 4th, 2007, 2:27pm hi all! I'm trying to project a cascode amplifier. I finished the schematic and now I'm working on the layout (never done before, God save me please..) here is my schematic: http://www.thebags.it--out-of-date/listing/layout/01/schem.png here is the entire layout I designed http://www.thebags.it--out-of-date/listing/layout/01/layout_tutto.png and some relevant particulars: - M1 and IN1 http://www.thebags.it--out-of-date/listing/layout/01/M1.png - connection between M1 and M0 and IN0 http://www.thebags.it--out-of-date/listing/layout/01/conn_m1_m0.png - connection between M0 and the resistance connected to vdd http://www.thebags.it--out-of-date/listing/layout/01/resistance_m0.png (Do you think my layout should match the schematic? take a look to the pins ..I'm not sure they are ok) 1.: I run VRC and it sad only something about the density of my MET1 and POLY1 areas ..I didn't care ..hope I was right 2.:Then I extracted the circuit and run LVS ..LVS does not recongnise that I mad my MOS with 13 gates instead of one and give me some errors about it. Then there are some errors I'm not able to understand ..here it is: Quote:
I run a simulation on the extracted circuit but the result is horrible ..it's another circuit :( can give me some suggestion about my layout? am I making some big mistakes? thank you all! matteo |
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