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Design >> Analog Design >> Schematic vs. Post-Lay simulation
https://designers-guide.org/forum/YaBB.pl?num=1181070778

Message started by eng on Jun 5^th, 2007, 12:12pm

Title: Schematic vs. Post-Lay simulation
Post by eng on Jun 5^th, 2007, 12:12pm

Hi,
I'm monitoring output DC voltage (CM) of a fully differencial opamp. In the schematic simulation both Voutp and Voutn are 675 mV however the post layout simulation gives Voutp=600 mV and Voutn= 740mV. What might cause this difference?
any comments?

Thanks

Title: Re: Schematic vs. Post-Lay simulation
Post by didac on Jun 5^th, 2007, 12:24pm

Hi,
This is probably caused by assymetries between branches in your layout.
Do they "see" the same length?
One branch has extra crossings than the other?
Check this kind of things and try to do a symmetric layout, it will help also in silicon step.
Good luck,

Title: Re: Schematic vs. Post-Lay simulation
Post by eng on Jun 5^th, 2007, 12:39pm

Hi didac,
Thanks for the reply.
The tried to make layout as symmetric as possible plus it's a dc voltage.
Do you think it is still a symmetry problem?

thanks

Title: Re: Schematic vs. Post-Lay simulation
Post by didac on Jun 5^th, 2007, 12:44pm

Well if you performed a R extraction and the asymmetry is significative it could happen but you are probably right that the cause it's another. In such cases I usually check the DC biasing points and try to debug from here,keep in touch.
Good luck.

Title: Re: Schematic vs. Post-Lay simulation
Post by eng on Jun 5^th, 2007, 1:37pm

Didac,
You're right. I extracted without setting any parasitic switch, the DC levels are exactly same as schematic (675 mV). Then I did extraction with all switches except R parasitic, still DC levels are same. So R parasitic extraction causes this difference. (600 mV & 750 mV)
Here is my design details;
My design is at 0.18 um RF CMOS (6 metal layers). The total area of OPAMP is 90x130 including CMFB, compansetion etc. I'm only using M1 and M2 layers for routing. and metal widths range from 480nm (very few) to 1 um. (mostly around 800nm)
As I said before I tried to make the layout as symmetric as possible as seen in the picture below.
I need your suggestions on how to overcome this issue.

thanks

Title: Re: Schematic vs. Post-Lay simulation
Post by ACWWong on Jun 5^th, 2007, 2:15pm

does your back extraction tool allow back annotation ? That way you can easy see where the parasitic R is coming into play...
Otherwise you can resort to inspecting the netlist to identify the parasitic resistors added (and to which nets) in the layout extraction process and identify the ones which are causing you the problem.
Anyway you can also do a quick sanity check by considering the intended I*R drops used in your circuit and the likely resistance of the M1 or M2 (&via) routing. Using a rule of thumb of 0.1 ohm/sq for the metal, a 100um length at 0.5um width is only 20 ohms... is your circuit sensitive to this ?? or are the kit R extraction rules wrong ??

Title: Re: Schematic vs. Post-Lay simulation
Post by didac on Jun 5^th, 2007, 11:10pm

Hi,
I agree with mr.Wong, perform a backannotation at the schematic is very useful to see the effects at each node. I also agree with the fact that maybe R extraction rules are not always reliable(i've seen from different foundries strange behaviours). As I can see in the attached file the layout is apparently symmetric, one thing that you can check is the number of vias used,i.e. in one track you put 2 vias to make a change and in the symmetric one you only put one(I incurred in this error too and then starts the long debuggin hours) so the equivalent resistance(not shown in parasitics) is bigger.
Good luck,keep in touch

Title: Re: Schematic vs. Post-Lay simulation
Post by eng on Jun 6^th, 2007, 9:37am

Hi,
What is the back annotation and how can I do it?

Title: Re: Schematic vs. Post-Lay simulation
Post by eng on Jun 6^th, 2007, 11:40am

Dear didac and acwwong, I just found the problem. I was placing the vdd pin at top-right and gnd pin at bottom-left of layout which messes up all the symmetry. I put them in the middle, now Voutp=675 mV and Voutn=674.9mV.
But I really wonder what back annotation is and how to perform it?

thanks

Title: Re: Schematic vs. Post-Lay simulation
Post by didac on Jun 6^th, 2007, 11:51am

The backannotation is an option that "prints" the values of the parasitics in the schematic so you can easily view at each node of the schematic the value of the parasitics. The way to perform this backannotation depends on the extractor(Assura,Calibre etc...), take a look at your documentation. I'm glad that you found the error.
As a side note have you performed an AC analysis?Just to check the effects of the capacitances.
Good luck with your designs.