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Design Languages >> Verilog-AMS >> how to model the nonidealities of opamp?verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1181500283

Message started by senyou78 on Jun 10^th, 2007, 11:31am

Title: how to model the nonidealities of opamp?verilog-A
Post by senyou78 on Jun 10^th, 2007, 11:31am

hi,
I do some research in delta-sigma modulator,I m using verilog-A and cadence.I want to model the nonidealities of a differential opamp that I am using in my circuit,I don´t know how to model that in verilog-A !using the macromodel of diff-opamp(like the the input/output resistance of the opamp.
is their any good coding which help me to analyse the non-idealities of the opamp?
thanks

Title: Re: how to model the nonidealities of opamp?verilo
Post by boe on Jun 11^th, 2007, 5:23am

hchanda posted a nice model (OK, it's single-ended, so you'll have to add the differential output): http://www.designers-guide.org/Forum/YaBB.pl?num=1165362179/5#5.

Title: Re: how to model the nonidealities of opamp?verilo
Post by senyou78 on Jun 11^th, 2007, 12:06pm

thanks
I ll try it ;)