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Design Languages >> Verilog-AMS >> chain of mosfet in verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1181642337

Message started by Darius on Jun 12^th, 2007, 2:58am

Title: chain of mosfet in verilog-A
Post by Darius on Jun 12^th, 2007, 2:58am

Hello!!! This website is wonderful!
I'm working with a "chain" of mos and I created a module for the instance of child model like this:

mos m1 (.g(gate), .d(d1), .s(source));
mos m2 (.g(gate), .d(d2), .s(d1));
mos m3 (.g(gate), .d(drain), .s(d2));
but :
1)how to plot the outputs of single mosfet like each gate current or charges?
2)how is possible to decide from simulator netlist if to connect 2 or 3 mosfets in the chain?(I'm thinking about if or case statement but this block is outside the "analog begin" and this solution doesn't work.
Please, can you help me?
Best Regard to all!
Darius :)

Title: Re: chain of mosfet in verilog-A
Post by Geoffrey_Coram on Jun 12^th, 2007, 4:07am

Darius wrote on Jun 12^th, 2007, 2:58am:

1)how to plot the outputs of single mosfet like each gate current or charges?

This is a simulator-specific implementation detail; your simulator may or may not provide access to that information, and you'll have to read the documentation to find out how to get it.

Quote:

2)how is possible to decide from simulator netlist if to connect 2 or 3 mosfets in the chain?(I'm thinking about if or case statement but this block is outside the "analog begin" and this solution doesn't work.

I think what you want is presently not possible within the language (there's ongoing work in the committee to permit the "generate" construct to do this).

However, you might be able to get similar behavior by setting up the chain for the longest length you might want, and then use a parameter to select how to short out the chain.

Code:

module moschain(drain, gate, source);
//...
parameter integer short_to = 0 from [0:2];
mos m1 (.g(gate), .d(d1), .s(source));
mos m2 (.g(gate), .d(d2), .s(d1));
mos m3 (.g(gate), .d(drain), .s(d2));
analog begin
if (short_to == 1)
V(d1,source) <+ 0;
else if (short_to == 2)
V(d2, source) <+ 0;
end
endmodule

If short_to == 2, then d2 will short to source, and only "m3" will be active. If short_to == 0, then the LRM specifies that the default for the branches is zero flow, meaning that there are no shorts, and the current has to flow through all 3 mosfets.

Title: Re: chain of mosfet in verilog-A
Post by Darius on Jun 12^th, 2007, 10:13am

Darius wrote on Jun 12^th, 2007, 2:58am:

1)how to plot the outputs of single mosfet like each gate current or charges?

This is a simulator-specific implementation detail; your simulator may or may not provide access to that information, and you'll have to read the documentation to find out how to get it.

I use simucad smartspice version 2.24.3.R and I didn't find yet this property in the documentation.

I have also convergence problem with chain for gate voltage>0.8, it's possible to be a problem because I use a chain? I'm not able to reach it.

Tank'u for reply, second answer is a smart idea ;)

Best regard

Dario

Title: Re: chain of mosfet in verilog-A
Post by Geoffrey_Coram on Jun 13^th, 2007, 6:01am

Darius wrote on Jun 12^th, 2007, 10:13am:

Darius wrote on Jun 12^th, 2007, 2:58am:

I use simucad smartspice version 2.24.3.R and I didn't find yet this property in the documentation.

Can't say I've ever used Verilog-A in smartspice, and my experience with that simulator in general is very limited.

[quote]I have also convergence problem with chain for gate voltage>0.8, it's possible to be a problem because I use a chain? I'm not able to reach it.

Very strange! I assume you can make the same chain in a regular spice netlist; does it work there?

Title: Re: chain of mosfet in verilog-A
Post by Darius on Jun 14^th, 2007, 5:57am

Darius wrote on Jun 12^th, 2007, 2:58am:

[quote]
Very strange! I assume you can make the same chain in a regular spice netlist; does it work there?

I tried to do the same chain in regular spice netlist but I don't know how to do...
My code is

Code:

YVLGBmos 1 2 3 Bmos
.model m_Bmos VLG MODULE=Bmos
Xm_Bmos g d s Bchain

.subckt Bchain g d s
m_Bmos1 g d1 s Bmos
m_Bmos2 g d d1 Bmos
.ends Bchain

X g d s Bchain

vgate g 0 dc 4
vdrain d 0 dc 0
vsource s 0 dc 0
...

I think it's bad, I don't have many experience ...

I tried also to do the verilog chain with another mos module and it work, so it can be that my module have some problem?

Title: Re: chain of mosfet in verilog-A
Post by Geoffrey_Coram on Jun 15^th, 2007, 5:15am

Darius wrote on Jun 14^th, 2007, 5:57am:

I tried also to do the verilog chain with another mos module and it work, so it can be that my module have some problem?

Seems likely to me. Did you try running some basic i-v curves on the module that has problems?

Title: Re: chain of mosfet in verilog-A
Post by Darius on Jun 15^th, 2007, 6:08am

Geoffrey_Coram wrote on Jun 15^th, 2007, 5:15am:

[quote author=Darius link=1181642337/0#4 date=1181825879]
Seems likely to me. Did you try running some basic i-v curves on the module that has problems?

Yes, the module works regularly alone.
With chain it doesn't reach the convergence of intermediate nodes voltages.
But the code for the spice chain has some problems? :'(