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Design Languages >> Verilog-AMS >> Reshaping transitions in veriloga voltage sources
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Message started by afisher on Jun 13^th, 2007, 5:04am

Title: Reshaping transitions in veriloga voltage sources
Post by afisher on Jun 13^th, 2007, 5:04am

Hi all,

I refer my question to veriloga voltage sources, generally full-swing, but not only.

The default veriloga shapes of voltage signals at the transition points is something that looks like 1st order polynom. This might cause convergence problems in some cases, as well as large CPU resources due to non-continuoues derivative of the signal.

Does anyone has a "shaper" solution/equation for solving these "ugly" part of the voltage signals?

Thanks in advance,
afisher.

Title: Re: Reshaping transitions in veriloga voltage sour
Post by Geoffrey_Coram on Jun 13^th, 2007, 6:04am

afisher wrote on Jun 13^th, 2007, 5:04am:

Hi all,

I refer my question to veriloga voltage sources, generally full-swing, but not only.

What is a "veriloga voltage source"?? Do you mean a voltage source from Annex E, which tells you how to instantiate voltage sources from a Spice simulator? In that case, it's your job to pick a well-behaved source. Eg, PWL is continuous but its derivatives are not, but that's not Verilog-A's fault.

Otherwise, you can write a voltage source directly in Verilog-A, and it's completely in your hands how you write the output voltage as a function of time.

-Geoffrey