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Design Languages >> Verilog-AMS >> How to remove noise(glitch) from digital input?
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Message started by seefree on Jun 13^th, 2007, 11:24am

Title: How to remove noise(glitch) from digital input?
Post by seefree on Jun 13^th, 2007, 11:24am

Hi there,

If I have a digital pulse input with different pulse widths, how can I remove the pulses smaller than a specific value, ex. 5us, in Verilog-AMS?

Thanks a lot,

Title: Re: How to remove noise(glitch) from digital input
Post by Marq Kole on Jul 23^rd, 2007, 5:45am

That depends on the specific signals. In case of a digital signal you can use a transition function with a delay of 5 μs so the transition of the rise will be negated by the transition of the fall. In case of an analog signal you can use the slew function to limit the maximum slope of the signal, although a remnant of the glitch with reduced amplitude will still be visible.

I think it is not possible to do this without the implicit delay of 5 μs as the simulator will otherwise not be able to recognize the glitch as such.

If you want a glitch of 5.0 μs to be filtered and one of 5.1 μs to pass, however, the above solution will not work. Then you need to specifically check that a signal with a delay of 5 μs has the same value as the "undelayed" version of the signal and then choose whether or not to reproduce the delayed signal.