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Design >> Analog Design >> Class AB output stage analysis
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Message started by adesign on Jun 14^th, 2007, 1:12am

Title: Class AB output stage analysis
Post by adesign on Jun 14^th, 2007, 1:12am

Dear all,

Please have a look at the attached "Class-AB output stage" circuit.
In this circuit,
(W/L)₄=(W/L)₉,
(W/L)₃=(W/L)₈

How do we ensure that current through M6 is equally divided between M3 and M4?

Also why

v2=v3,
v1=v4???

Please comment.

Best Regards,

Title: Re: Class AB output stage analysis
Post by monte78 on Jun 14^th, 2007, 1:22am

Hi!

I had similar questions short time ago, take a look to the following presentation (slide 15 up to the end):

http://amesp02.tamu.edu/~sanchez/607%20Lect%204%20Line%20Driver%20Design.pdf

The current will divide into two eaqual parts if the gm of the NMOS and PMOS transistors is equal.
However any other comment would be useful also for me.

Bye,

Monte

Title: Re: Class AB output stage analysis
Post by yvkrishna on Apr 12^th, 2010, 10:48am

hi guys,

i too have the same doubt. how to bias such that equal currents flow through M3,M4 ?

and how will having same 'gm do that? please elaborate

Thanks,
yvkrishna

Title: Re: Class AB output stage analysis
Post by loose-electron on Apr 15^th, 2010, 12:10am

gm of M3, M4 will not match. Not without some intelligent control or feedback to make it happen.

Not a good circuit architecture IMHO

Title: Re: Class AB output stage analysis
Post by yvkrishna on Oct 5^th, 2010, 4:56am

hi all,

does any one have some more understanding of this issue in biasing class AB structure?

especially how can we ensure that currents divide equally (M3,M4)with process variations ?

many thanks for the replies.

-yvkrishna

Title: Re: Class AB output stage analysis
Post by sli103105 on Oct 7^th, 2010, 8:53am

IMHO, it's easier to put this into some Amplifier in feedback loop.

As it's already been pointed out, there're 2 TL loops
1) M9,10,4,2
2) M7,8,3,1

M6 is the bias current source and Vin will be adjusted by
the feedback loop such that current through M1 and M2
will be equal so that Vout stays around mid-rail. When that
happens, current through M3,4 will be roughly equal as well,
i.e., both equal to Ib roughly.

Title: Re: Class AB output stage analysis
Post by Alexandar on Oct 8^th, 2010, 3:49am

I wonder how accurate this will be, with regard to drain source modulation.