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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> jitter simulation for a 16 bit ADC https://designers-guide.org/forum/YaBB.pl?num=1182112854 Message started by analog2000 on Jun 17th, 2007, 1:40pm |
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Title: jitter simulation for a 16 bit ADC Post by analog2000 on Jun 17th, 2007, 1:40pm Hi, I am designing a vco for a 16 bit ADC. Can some one tell me what frequency offsets I should use to simulate jitter for a 16 bit ADC ? thanks analog2000 |
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Title: Re: jitter simulation for a 16 bit ADC Post by ywguo on Jun 19th, 2007, 7:46pm Hi, I am not clear what is your question. What is your spec/requirement on the clock for your 16bit ADC? I don't know the reason why you simulate jitter with frequency offset. Yawei |
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Title: Re: jitter simulation for a 16 bit ADC Post by jeffyan on Jun 27th, 2007, 5:47pm analog2000 wrote on Jun 17th, 2007, 1:40pm:
hi plz have a look at these posts: http://www.designers-guide.org/Forum/YaBB.pl?num=1166075659 |
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