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Design >> Analog Design >> low voltage design technique
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Message started by jeremy_zhu on Jun 19^th, 2007, 4:37am

Title: low voltage design technique
Post by jeremy_zhu on Jun 19^th, 2007, 4:37am

i'm trying to design a ultra-low voltage opa . the model i used to design it is a typical 0.5um CMOS model whose Vtn≈0.85(w/l 20/0.5) ,Vtp≈0.95(w/l 20/5.5), but my supply voltage is only sub-1v(0.9 or less). the opa must satisfy the specifications:>80dB 10~20Mhz GBW and constant gm with rail to rail ICMR. i want to know whether it can be realized for the model by some special technique :FG ,BULK-DRIVEN or some other ones.
any special comments ,suggestions or useful references?

Title: Re: low voltage design technique
Post by carlgrace on Jun 27^th, 2007, 5:30am

Bulk driven will be very hard to meet specs. You will probably want to do a two stage op amp, with two input diff pairs, one is NMOS and one is PMOS. A very good book to get started is Laker and Sansen. You can also search for rail-to-rail input stages on Google.

good luck,
Carl

Title: Re: low voltage design technique
Post by vivkr on Jul 11^th, 2007, 3:03am

jeremy_zhu wrote on Jun 19^th, 2007, 4:37am:

Hi Jeremy,

While bulk-driven techniques may be not be optimal for your specs, you can certainly try to reduce the threshold voltages of your transistors by applying a
small forward-bias to the bulk-source junction. Needless to say, this is fraught with peril in case you latchup.

Regards
Vivek

Title: Re: low voltage design technique
Post by JD on Aug 20^th, 2007, 3:21pm

No, it won't work unless you lower vtn and vtp. If your vdd < |vtn| + |vtp|, bulk driving maybe the only way to go.