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Modeling >> Behavioral Models >> Usage of already simulated results
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Message started by Prathap on Jun 21^st, 2007, 4:45am

Title: Usage of already simulated results
Post by Prathap on Jun 21^st, 2007, 4:45am

Hi,
I just wanted to know whether usage of already available simulations results is possible in Verilog A. Like for instance giving the available results as an input to one of the input ports in a Verilog A module.

To be more tool specific, one knows that the simulation results get stored as a 'psf' file in a Cadence environment. So is there any possibilty to include the psf data as a file to make it the source of a input port.

Thanks,
Prathap.

Title: Re: Usage of already simulated results
Post by sheldon on Jun 21^st, 2007, 5:36am

Prathap,

Look at the vpwlf source in analogLib. You can attach an ASCII file to
the source and use it as an input. You can use Wavescan's Table function
to write out the data.

Best Regards,

Sheldon

Title: Re: Usage of already simulated results
Post by Prathap on Jun 30^th, 2007, 5:06am

Thanks a lot Sheldon. I'll try it and get back to you if there are some doubts.

Title: Re: Usage of already simulated results
Post by Unique on Jul 4^th, 2007, 5:31am

Do You have to use exactly cadence program? May be it is worth probing some other simulators, cheaper and easier in terms of maintenance? I mean in this case You will have an opportunity to ask support team any questions.

Title: Re: Usage of already simulated results
Post by Prathap on Jul 9^th, 2007, 6:06am

Well, right now we are working only in the cadence environment. We havent tried probing other simulators as of yet. Anyway maybe we can look into that option too ;)

Title: Re: Usage of already simulated results
Post by Prathap on Jul 25^th, 2007, 3:34am

Hi All (again!!),

As Sheldon had suggested i indeed looked into the "vpwlf" source in the ahdlLib. But following is what i actually understood from using it :

The "vpwlf" source uses a file as its input; a file which contains two parameters - TIME and VOLTAGE. the file looks like this:
time Volt
-----------------
0 0
0.5 1
1 2

the "vpwlf" works fine if its input file is in a format as specified above. I even tried using the Table function and saving the results as a ".csv" format. Actually this answers only half of my question. I'll describe my other half of my question in detail so that it may help in getting the answer.

Consider I'm using an 8-bit ADC (either a transistor level circuit or a Verilog A model). Also consider that the outputs from the ADC are fed to a 2's complement block. What i really want to do here is that i need to store the output values of the ADC in a file so that i can use it in future. In a Cadence environment the results get stored as a ".psf" format. Now in the intention of optimising memory and time i would like to use the ".psf" file as an input to the 2's complement.
The main reason being time here. I thought that if we could use the already simulated results it could help us in saving a considerable amount of time. Hence in the above example i need not simulate the ADC again; i just can use the results which i had got from simulations sometime back.

Hence my question is whether is there any possibilty of making use of the ".psf" file and give it as an input to an input source. I actually tried doing this but unfortunately i got an error which stated that it could not find the psf file.

Prathap