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Design Languages >> Verilog-AMS >> How to model KT/C noise Verilog-A?
https://designers-guide.org/forum/YaBB.pl?num=1182503879

Message started by senyou78 on Jun 22^nd, 2007, 2:17am

Title: How to model KT/C noise Verilog-A?
Post by senyou78 on Jun 22^nd, 2007, 2:17am

hi everybody,
I want to analyse and see the effect of switched-capacitor kT/C noise(concerning studies of analog circuit non-idealities delta-sigma modulator),
so I need a module which implement kT/C in verilog-A.
I´m using verilog-A and cadence.
Any help would be greatly appreciated
thanks

Title: Re: How to model KT/C noise Verilog-A?
Post by Geoffrey_Coram on Jun 22^nd, 2007, 6:06am

You'll need to think harder about what you want to do.

kT/C noise comes from the kTR thermal noise of a resistor, band-limited by the 1/RC time constant. I don't think you can model this as a "noisy capacitor."

And it's also a little tricky to get the noise of a switched-capacitor circuit; you should probably read http://www.designers-guide.org/Analysis/sc-filters.pdf

Title: Re: How to model KT/C noise Verilog-A?
Post by senyou78 on Jun 27^th, 2007, 2:01am

How to add white noise to a model :(? i want to model the nonidealities of the first order (switched capacitor)delta-sigma modulator,I realized the circuit in verilog-A every module is written in verilog-A except the switch which is realized with transistor level(because I had lot of troubles with switch model).I allready modeled the non-ideality of the opamp(dc gain,slew rate,etc...),and now I want to implement the oder nonidealities concerning capacitor noise,thermal noise,switch...... :-/
is there any materials which could help me to anderstand and realize the non-idealities of D-S modulator?
thanks

Title: Re: How to model KT/C noise Verilog-A?
Post by Geoffrey_Coram on Jun 27^th, 2007, 3:59am

senyou78 wrote on Jun 27^th, 2007, 2:01am:

How to add white noise to a model :(?

Again, you need to think hard about what you're really going to do. You can add noise with the white_noise(pwr, "name") function, however, that only works for small-signal noise. I think for a sigma-delta converter, you need to simulate in the time domain, and thus you need to have a module that generates noise in the time domain, eg, generating samples on every timepoint. I don't know to what extent the simulators that do transient noise do the "right thing" with white_noise() in that context.