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Design Languages >> Verilog-AMS >> [q] In verilog-A
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Message started by Renekim on Jun 24^th, 2007, 5:28pm

Title: [q] In verilog-A
Post by Renekim on Jun 24^th, 2007, 5:28pm

Dear All,

In the verilog-A manual, it says "the procedural statements in a block statement are executed sequentially in the given order".
I thought all the statements were executed concurrently in the block (such as analog block).
Does this means the following two blocks are different?
1.
analog begin
@(timer( ...))
state = ( condition ) ? 1 : 0;

v(out) = state;
end
2.
analog begin
v(out) = state;

@(timer( ...))
state = ( condition ) ? 1 : 0;

end

Thank You

Title: Re: [q] In verilog-A
Post by Geoffrey_Coram on Jun 25^th, 2007, 5:33am

Yes, the blocks are different.

I assume you wanted
V(out) <+ state;

else your module just sets an internal variable.

The statements are evaluated sequentially, so you can also have:
x = 5;
x = 7 + V(in);
V(out) <+ x;
and have no ambiguity or race condition about what voltage is on the output.

I recall something about the analog block being evaluated "instantaneously" which may have been the source of your misconception; the solver may actually call the analog block repeatedly as it tries to converge at a timepoint, but this is transparent to the user, simulation time does not advance.

Title: Re: [q] In verilog-A
Post by Ken Kundert on Jun 25^th, 2007, 10:43am

The way I think of it is this: The analog block is evaluated every instant of time (this is not literally true, but it is the ideal towards which the simulator is striving). Within the analog block, the statements are evaluated sequentially, however unlike local variables, signals maintain their value over an instant in time. By signals I mean node and branch voltages and currents. So what I mean by this is that variables can take different values during the evaluation of an analog block, but signals always maintain the same value over the entire evaluation of the analog block.

-Ken