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Design Languages >> Verilog-AMS >> For statement condition error?
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Message started by sylak on Jun 25^th, 2007, 6:02pm

Title: For statement condition error?
Post by sylak on Jun 25^th, 2007, 6:02pm

I am trying to get my array output using a for statement.When I use an integer(mode) in the condition of for statement the simualtion aborts and gives me segmentation error.

for (i = 0; i < mode ; i = i +1) begin
V(dout[i] ) <+ transition( s [i] ? vlogic_high : vlogic_low, tdelay, trise, tfall);
end // for

I generate the "mode" inside the ' analog begin 'statements using if conditons

if (V(A)>vth && V(B)>vth) mode=4;
else if (V(A)>vth && V(B)<vth) mode=6;
else if (V(A)<vth && V(B)>vth) mode=3;
else if (V(A)<vth && V(B)<vth) mode=9;
else $display("Mode Specification error");

I cant figure out what is wrong in this piece of code. I have used 'for' statements before and have never had this problem. I also used (another set of ) for statements with this code in the way I described and it seems to work.

Would appreciate any insight.

Thanks

Title: Re: For statement condition error?
Post by Ken Kundert on Jun 25^th, 2007, 8:40pm

All segmentation errors represent bugs in the tool. You should report the problem to your tool vendor.

-Ken

Title: Re: For statement condition error?
Post by Geoffrey_Coram on Jun 26^th, 2007, 3:56am

While Ken is correct, that the segmentation fault is a bug in the simulator and should be reported, your code is not legal. (The simulation should tell you this rather than aborting.)

If you have a contribution V() <+ inside a for loop, then the condition is not allowed to depend on variables, only constants and parameters. Frequently, this sort of code will be written with a "genvar" instead of an integer as the loop index.

parameter integer maxmode = 9;
genvar g;
integer i, mode;
real vout[0:maxmode];

// code to set mode here

for (i = 0; i < mode; i = i + 1) begin
vout[i] = s[i] ? vlogic_high : vlogic_low;
end

for (g = 0; g < maxmode; g = g+ 1) begin
V(dout[g]) <+ transition( vout[i], tdelay, trise, tfall);
end

Title: Re: For statement condition error?
Post by sylak on Jun 26^th, 2007, 10:34am

Thanks Ken and Geoffrey,

I will talk to my tool vendor on this.

I had declared 'i' as genvar., 'mode' as an integer,
... and was using it in for loop(with 'mode' in condition) throught my code...Most of the code is inside a '@cross' statment. this is where I also assign a value to mode using if-else statments (I mentioned above)

s[0:maxmode] is declared as real and dout[0:maxmode] as voltgae and output

The assignment of V(dout[i]) is the only thing that remains outsidethe' @cross' statement.This is the only time the tool comlpains if I use the 'mode' in the V(dout[i]) transition statement. If I replace the 'mode' at this point with a number...it works fine...As I said I have used 'mode' a number of different times within the code in the same format.

In this case ...Do you still think it is a tool problem and nothing to do with how verilog-A sees the statement?

Title: Re: For statement condition error?
Post by Geoffrey_Coram on Jun 27^th, 2007, 3:55am

sylak wrote on Jun 26^th, 2007, 10:34am:

In this case ...Do you still think it is a tool problem and nothing to do with how verilog-A sees the statement?

A segmentation fault is ALWAYS a tool problem. It's a programming error, because the tool should have given you a decent error message so you'd know how to fix it. Presumably, you would then get a message about how the vendor interprets the LRM and why they believe your statement is illegal.

Again, the problem is that the for() conditions need to be constants because of what's inside; you might get away with the contribution V() <+ but certainly the analog transition() operator is not allowed. (I should go back and re-read the LRM; I know you can have a switch branch, where the if() condition depends on a variable and have contributions inside, so it seems that the same should apply to for() loops. On the other hand, I know I've seen problems with N-bit converter models that use for() loops; maybe it's always because of the transition() operator.)

Title: Re: For statement condition error?
Post by Riad KACED on Nov 5^th, 2009, 12:23pm

Hi Geoffrey and All,

The genvars are giving me some hard times these days. I was mainly confused because it appears like genvars are not supported the same way in VerilogD and VerilogAMS (http://www.verilog.org/mantis/view.php?id=812).

My current understanding with genvars in Verilog-AMS is they must be used as index of for loops in the following couple of cases:

1. Access to the analog signals in busses from within analog processes.
2. When analog operators (like transition) are invoked in a for loop

However, you have stated above:

Quote:

If you have a contribution V() <+ inside a for loop, then the condition is not allowed to depend on variables, only constants and parameters.

Is the above statement part of the VAMS LRM ?
Would you expect the following loop to be needing i as genvar (although this is unlikely to be a real world example) ?

analog begin
for(i=0; i<3; i=i+1)
V(myAnalogNode) <+ i;
end

Thank you very much in advance for enlightening me.

Cheers,
Riad.

Title: Re: For statement condition error?
Post by Geoffrey_Coram on Nov 6^th, 2009, 12:05pm

No, that example shouldn't need a genvar.

The LRM contains a switch branch example:

if (V(in) > vth)
V(out) <+ 0;
else
I(out) <+ 0;

so clearly one can have even voltage-dependent quantities in the condition.

Title: Re: For statement condition error?
Post by Riad KACED on Nov 9^th, 2009, 11:56am

Hi Geoffrey,

OK, that's very clear now !
I suppose the example you have given is wrapped in a for loop although I don't see any use of the loop index in your code (I couldn't find this code in the LRM btw, would you mind posting the page/lrm_version ?).

Anyway, things are clearer now.

Thanks again for your comments,
Cheers,
Riad.

Title: Re: For statement condition error?
Post by Geoffrey_Coram on Nov 30^th, 2009, 3:52pm

Ah, no, my example doesn't use a for-loop, but the restrictions on the conditionals for-loops and if-blocks are essentially the same.