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Other CAD Tools >> Physical Verification, Extraction and Analysis >> LVS with Standard Cell Libraries
https://designers-guide.org/forum/YaBB.pl?num=1182859435

Message started by mtpank on Jun 26^th, 2007, 5:03am

Title: LVS with Standard Cell Libraries
Post by mtpank on Jun 26^th, 2007, 5:03am

Does anyone know how to get standard cells through lvs??

I'm drawing a mixed-mode design vith virtuoso XL and would like to use digital standard cells provided by vendor.
For these standard cells vendor provides layout views that have only diffusion, n-well and metal1 layers + pins visible.
I'm using calibre to do LVS checks.

Problem arises when calibre tries to extract the standard cells. More precisely, it cannot recognize standard cells.
I guess, it is trying to compare them on the transistor level, but fails because the layout views are incomplete.
I've tried to turn on recognize all gates option from LVS options Gates tab, but this doesn't help.
There must be a way to tell LVS checker that standard cells are OK, do not bother to check them, but how to do this?

Title: Re: LVS with Standard Cell Libraries
Post by mtpank on Jun 28^th, 2007, 3:09am

:D ...found it myself. Careful examination of Calibres user manual paid off.
So here is the solution for all interested.

You have to merge standard cells as black boxes to the LVS rule file.
For example:
LVS BOX A_lay A_src
where A_lay is the layout view and A_src is the schematic view of a given standar cell.

Note. Power pin name mismatches are still possible due to inherited power pin names used in standard cell libraries.