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Design Languages >> Verilog-AMS >> Help with test bench
https://designers-guide.org/forum/YaBB.pl?num=1183386330

Message started by slackjack on Jul 2^nd, 2007, 7:25am

Title: Help with test bench
Post by slackjack on Jul 2^nd, 2007, 7:25am

Hey all,

I'm currently learning verilog. I'm trying to make a test bench to
simulate a binary-to-7-segment decoder. I've broken the circuitry up
into individual logic circuits for each segment (a-g); so I have 7
logic circuits total.

I want to see how each of these individual logic circuit would respond
to a series of identical waveforms. So instead of making separate
verilog files for each of the logic circuits, I decided to dump them
all in a test bench. But in doing so, I've made some mistakes and cant
figure out what they are.

I'm not concerned (ATM) with whether the logic circuits are functionally correct, right
now I want to get the test bench up and running. Please help.

Thanks :)

Code:

module testBench;

wire [6:0] w1;
wire w2,w3,w4,w5;

binaryToASeg a(w1[6],w2,w3,w4,w5);
binaryToBSeg b(w1[5],w2,w3,w4,w5);
binaryToCSeg c(w1[4],w2,w3,w4,w5);
binaryToDSeg d(w1[3],w2,w3,w4,w5);
binaryToESeg e(w1[3],w2,w3,w4,w5);
binaryToFSeg f(w1[1],w2,w3,w4,w5);
binaryToGSeg g(w1[0],w2,w3,w4,w5);
Func_gen_and_disp disp(w2,w3,w4,w5,w1);

endmodule

module binaryToASeg //Segment A
(input b3, b2, b1, b0,
output aSeg);

and g4(aSeg,~bo,~b3,b2);

endmodule

module binaryToBSeg //Segment B
(input b3,b2,b1,b0,
output bSeg);

and g1(p1,~b1,b0,~b3);
and g2(p2,b1,~b0,~b3,b2);
or g3(bSeg,p1,p2);

endmodule

module BinaryToCSeg //Segment C
(input b3, b2, b1, b0,
output cSeg);

and g1(p1,~b3,~b2,~b1,b0);
and g2(p2,~b3,~b2,b1,~b0);
or g3(cSeg, p1,p2);

endmodule

module BinaryToDSeg //Segment D
(input b3, b2, b1, b0,
output dSeg);

and g1(p1,~b3,b2,~b1,~b0);
and g2(p2,b3,~b2,~b1,b0);
and g3(p3,~b3,b2,b1,b0);
or g4(dSeg,p1,p2,p3);

endmodule

module BinaryToESeg //Segment E
(input b3, b2, b1, b0,
output eSeg);

and g1(p1,~b3,b1,b0);
and g2(p2,~b3,b2,~b1);
and g3(p3,b3,~b2,~b1,b0);
or g4(eSeg,p1,p2,p3);

endmodule

module BinaryToFSeg //Segment F
(input b3, b2, b1, b0,
output fSeg);

and g1(p1,b1,~b3,~b2);
and g2(p2,b1,b0,~b3);
or g3(fSeg,p1,p2);

endmodule

module BinaryToGSeg //Segment G
(input b3, b2, b1, b0,
output gSeg);

and g1(p1,~b3,~b2,~b1,~b0);
and g2(p2,~b3,b2,b1,b0);
or g3(gSeg,p1,p2);

endmodule

module Func_gen_and_disp //here is where I make the waveform and
//print the results.
(output reg b3,b2,b1,b0,
input [6:0] Seg);

initial

begin

$monitor
($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b,
bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b,",
b3,b2,b1,b0,
Seg[6],Seg[5],Seg[4],Seg[3],Seg[2],Seg[1],Seg[0]);

#10 b3 = 0; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 1;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 1;
#10 $finish;
end

endmodule

P.S. Remember that I'm new to the world of verilog, so if you have any suggestions on how to do this in a more efficient way, please do tell.

Title: Re: Help with test bench
Post by slackjack on Jul 5^th, 2007, 7:41am

No comments on this guys?

Title: Re: Help with test bench
Post by boe on Jul 6^th, 2007, 4:55am

Hi slackjack,
1. Verilog is case sensitive, so you can't mix BinaryToCSeg and binaryToCSeg (etc).
2. the binaryToXSeg's have their output as lat port, but in the instantiation you give the output first.

BOE.

Title: Re: Help with test bench
Post by Geoffrey_Coram on Jul 6^th, 2007, 5:04am

Quote:

binaryToASeg a(w1[6],w2,w3,w4,w5);

module binaryToASeg //Segment A
(input b3, b2, b1, b0,
output aSeg);

It looks to me like you've swapped your inputs and outputs. That is, the module declarations always have the output last, but the instantiation lines always have w5 as the last port connection, meaning all the segments are fighting to set the value on w5.

I think you need:
binaryToASeg a(w2,w3,w4,w5, w1[6]);
etc.

Title: Re: Help with test bench
Post by slackjack on Jul 6^th, 2007, 6:35am

Thank you both for your responses. I've changed my code as per your suggestions.

Code:

module testBench;

wire [6:0] seg;
wire b3,b2,b1,b0;

binaryToASeg a(b3,b2,b1,b0,seg[6]);
binaryToBSeg b(b3,b2,b1,b0,seg[5]);
binaryToCSeg c(b3,b2,b1,b0,seg[4]);
binaryToDSeg d(b3,b2,b1,b0,seg[3]);
binaryToESeg e(b3,b2,b1,b0,seg[2]);
binaryToFSeg f(b3,b2,b1,b0,seg[1]);
binaryToGSeg g(b3,b2,b1,b0,seg[0]);
Func_gen_and_disp disp(b3,b2,b1,b0,seg);

endmodule

module binaryToASeg //Segment A
(input b3, b2, b1, b0,
output aSeg);

and g4(aSeg,~bo,~b3,b2);

endmodule

module binaryToBSeg //Segment B
(input b3,b2,b1,b0,
output bSeg);

and g1(p1,~b1,b0,~b3);
and g2(p2,b1,~b0,~b3,b2);
or g3(bSeg,p1,p2);

endmodule

module binaryToCSeg //Segment C
(input b3, b2, b1, b0,
output cSeg);

and g1(p1,~b3,~b2,~b1,b0);
and g2(p2,~b3,~b2,b1,~b0);
or g3(cSeg, p1,p2);

endmodule

module binaryToDSeg //Segment D
(input b3, b2, b1, b0,
output dSeg);

and g1(p1,~b3,b2,~b1,~b0);
and g2(p2,b3,~b2,~b1,b0);
and g3(p3,~b3,b2,b1,b0);
or g4(dSeg,p1,p2,p3);

endmodule

module binaryToESeg //Segment E
(input b3, b2, b1, b0,
output eSeg);

and g1(p1,~b3,b1,b0);
and g2(p2,~b3,b2,~b1);
and g3(p3,b3,~b2,~b1,b0);
or g4(eSeg,p1,p2,p3);

endmodule

module binaryToFSeg //Segment F
(input b3, b2, b1, b0,
output fSeg);

and g1(p1,b1,~b3,~b2);
and g2(p2,b1,b0,~b3);
or g3(fSeg,p1,p2);

endmodule

module binaryToGSeg //Segment G
(input b3, b2, b1, b0,
output gSeg);

and g1(p1,~b3,~b2,~b1,~b0);
and g2(p2,~b3,b2,b1,b0);
or g3(gSeg,p1,p2);

endmodule

module Func_gen_and_disp //here is where I make the waveform and print the results.
(output reg b3,b2,b1,b0,
input [6:0] Seg);

initial

begin

$monitor($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b, bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b,",b3,b2,b1,b0,Seg[6],Seg[5],Seg[4],Seg[3],Seg[2],Seg[1],Seg[0]);

#10 b3 = 0; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 1;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 1;
#10 $finish;
end

endmodule

However, when I compile this (on VeriLogger Pro) and still get error messages:

Code:

test2.v: L18: error: parse error, unexpected INPUT_
test2.v: L19: error: parse error, unexpected OUTPUT
test2.v: L23: error: Invalid port name
test2.v: L26: error: parse error, unexpected INPUT_
test2.v: L27: error: parse error, unexpected OUTPUT
test2.v: L33: error: Invalid port name
test2.v: L36: error: parse error, unexpected INPUT_
test2.v: L37: error: parse error, unexpected OUTPUT
test2.v: L43: error: Invalid port name
test2.v: L46: error: parse error, unexpected INPUT_
test2.v: L47: error: parse error, unexpected OUTPUT
test2.v: L54: error: Invalid port name
test2.v: L57: error: parse error, unexpected INPUT_
test2.v: L58: error: parse error, unexpected OUTPUT
test2.v: L65: error: Invalid port name
test2.v: L68: error: parse error, unexpected INPUT_
test2.v: L69: error: parse error, unexpected OUTPUT
test2.v: L75: error: Invalid port name
test2.v: L78: error: parse error, unexpected INPUT_
test2.v: L79: error: parse error, unexpected OUTPUT
test2.v: L85: error: Invalid port name
test2.v: L88: error: parse error, unexpected OUTPUT
test2.v: L89: error: parse error, unexpected INPUT_
test2.v: L110: error: Invalid port name
Finished Phase I
Process exited with code 0.

Title: Re: Help with test bench
Post by boe on Jul 6^th, 2007, 6:49am

And in module binaryToASeg you should schange bo to b0.

BOE

Title: Re: Help with test bench
Post by slackjack on Jul 6^th, 2007, 6:53am

Hi Boe,

That didn't do the trick either. Does it have something to do with how I made module Func_gen_and_disp?

Title: Re: Help with test bench
Post by boe on Jul 6^th, 2007, 7:03am

I tried it with the attached code. And the simulation runs...

Code:

module testBench;

wire [6:0] seg;
wire b3,b2,b1,b0;

binaryToASeg a(b3,b2,b1,b0,seg[6]);
binaryToBSeg b(b3,b2,b1,b0,seg[5]);
binaryToCSeg c(b3,b2,b1,b0,seg[4]);
binaryToDSeg d(b3,b2,b1,b0,seg[3]);
binaryToESeg e(b3,b2,b1,b0,seg[2]);
binaryToFSeg f(b3,b2,b1,b0,seg[1]);
binaryToGSeg g(b3,b2,b1,b0,seg[0]);
Func_gen_and_disp disp(b3,b2,b1,b0,seg);

endmodule

module binaryToASeg //Segment A
(input b3, b2, b1, b0,
output aSeg);

and g4(aSeg,~b0,~b3,b2);

endmodule

module binaryToBSeg //Segment B
(input b3,b2,b1,b0,
output bSeg);

and g1(p1,~b1,b0,~b3);
and g2(p2,b1,~b0,~b3,b2);
or g3(bSeg,p1,p2);

endmodule

module binaryToCSeg //Segment C
(input b3, b2, b1, b0,
output cSeg);

and g1(p1,~b3,~b2,~b1,b0);
and g2(p2,~b3,~b2,b1,~b0);
or g3(cSeg, p1,p2);

endmodule

module binaryToDSeg //Segment D
(input b3, b2, b1, b0,
output dSeg);

and g1(p1,~b3,b2,~b1,~b0);
and g2(p2,b3,~b2,~b1,b0);
and g3(p3,~b3,b2,b1,b0);
or g4(dSeg,p1,p2,p3);

endmodule

module binaryToESeg //Segment E
(input b3, b2, b1, b0,
output eSeg);

and g1(p1,~b3,b1,b0);
and g2(p2,~b3,b2,~b1);
and g3(p3,b3,~b2,~b1,b0);
or g4(eSeg,p1,p2,p3);

endmodule

module binaryToFSeg //Segment F
(input b3, b2, b1, b0,
output fSeg);

and g1(p1,b1,~b3,~b2);
and g2(p2,b1,b0,~b3);
or g3(fSeg,p1,p2);

endmodule

module binaryToGSeg //Segment G
(input b3, b2, b1, b0,
output gSeg);

and g1(p1,~b3,~b2,~b1,~b0);
and g2(p2,~b3,b2,b1,b0);
or g3(gSeg,p1,p2);

endmodule

module Func_gen_and_disp //here is where I make the waveform and print the results.
(output reg b3,b2,b1,b0,
input [6:0] Seg);

initial

begin

$monitor($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b, bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b,",b3,b2,b1,b0,Seg[6],Seg[5],Seg[4],Seg[3],Seg[2],Seg[1],Seg[0]);

#10 b3 = 0; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 1;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 1;
#10 $finish;
end

endmodule

Title: Re: Help with test bench
Post by slackjack on Jul 6^th, 2007, 7:11am

Thats weird. Are you using modelsim to run this?

Title: Re: Help with test bench
Post by boe on Jul 6^th, 2007, 7:18am

No, ncsim.
Perhaps you should try old syntax:

Code:

module binaryToASeg ( b3, b2, b1, b0, Seg); //Segment A
input b3, b2, b1, b0;
output aSeg;

instead of

Code:

module binaryToASeg //Segment A
(input b3, b2, b1, b0,
output aSeg);

Title: Re: Help with test bench
Post by slackjack on Jul 6^th, 2007, 7:49am

Old syntax yields nothing.

Code:

module testBench;

wire [6:0] seg;
wire b3,b2,b1,b0;

binaryToASeg a(b3,b2,b1,b0,seg[6]);
binaryToBSeg b(b3,b2,b1,b0,seg[5]);
binaryToCSeg c(b3,b2,b1,b0,seg[4]);
binaryToDSeg d(b3,b2,b1,b0,seg[3]);
binaryToESeg e(b3,b2,b1,b0,seg[2]);
binaryToFSeg f(b3,b2,b1,b0,seg[1]);
binaryToGSeg g(b3,b2,b1,b0,seg[0]);
Func_gen_and_disp disp(b3,b2,b1,b0,seg);

endmodule

module binaryToASeg (b3, b2, b1, b0,Seg);

input b3, b2, b1, b0;
output aSeg;

and g4(aSeg,~b0,~b3,b2);

endmodule

module binaryToBSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output bSeg;

and g1(p1,~b1,b0,~b3);
and g2(p2,b1,~b0,~b3,b2);
or g3(bSeg,p1,p2);

endmodule

module binaryToCSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output cSeg;

and g1(p1,~b3,~b2,~b1,b0);
and g2(p2,~b3,~b2,b1,~b0);
or g3(cSeg, p1,p2);

endmodule

module binaryToDSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output dSeg;

and g1(p1,~b3,b2,~b1,~b0);
and g2(p2,b3,~b2,~b1,b0);
and g3(p3,~b3,b2,b1,b0);
or g4(dSeg,p1,p2,p3);

endmodule

module binaryToESeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output eSeg;

and g1(p1,~b3,b1,b0);
and g2(p2,~b3,b2,~b1);
and g3(p3,b3,~b2,~b1,b0);
or g4(eSeg,p1,p2,p3);

endmodule

module binaryToFSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output fSeg;

and g1(p1,b1,~b3,~b2);
and g2(p2,b1,b0,~b3);
or g3(fSeg,p1,p2);

endmodule

module binaryToGSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output gSeg;

and g1(p1,~b3,~b2,~b1,~b0);
and g2(p2,~b3,b2,b1,b0);
or g3(gSeg,p1,p2);

endmodule

module Func_gen_and_disp (b3,b2,b1,b0,Seg);
output b3,b2,b1,b0;
input [6:0] Seg;

initial

begin

$monitor($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b, bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b,",b3,b2,b1,b0,Seg[6],Seg[5],Seg[4],Seg[3],Seg[2],Seg[1],Seg[0]);

#10 b3 = 0; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 1;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 1;
#10 $finish;
end

endmodule

I'll have to try this on Icarus Verilog or modelsim. This is beginning to prove very frustrating and is confusing me even more about the language.

Title: Re: Help with test bench
Post by slackjack on Jul 6^th, 2007, 8:02am

I've just confirmed that veriLogger pro doesnt use verilog 2001 style syntax.

Title: Re: Help with test bench
Post by boe on Jul 6^th, 2007, 8:27am

Hi slackjack,
I noticed you have Seg in the port list but aSeg in the output statement...
BOE

Code:

module binaryToASeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output aSeg;

Title: Re: Help with test bench
Post by slackjack on Jul 6^th, 2007, 9:00am

I made the changes. Does this look alright, becuase it still doesnt compile:

Code:

module testBench;

wire [6:0] Seg;
wire b3,b2,b1,b0;

binaryToASeg a(b3,b2,b1,b0,Seg[6]);
binaryToBSeg b(b3,b2,b1,b0,Seg[5]);
binaryToCSeg c(b3,b2,b1,b0,Seg[4]);
binaryToDSeg d(b3,b2,b1,b0,Seg[3]);
binaryToESeg e(b3,b2,b1,b0,Seg[2]);
binaryToFSeg f(b3,b2,b1,b0,Seg[1]);
binaryToGSeg g(b3,b2,b1,b0,Seg[0]);
Func_gen_and_disp disp(b3,b2,b1,b0,Seg);

endmodule

module binaryToASeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g4(Seg,~b0,~b3,b2);

endmodule

module binaryToBSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g1(p1,~b1,b0,~b3);
and g2(p2,b1,~b0,~b3,b2);
or g3(Seg,p1,p2);

endmodule

module binaryToCSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g1(p1,~b3,~b2,~b1,b0);
and g2(p2,~b3,~b2,b1,~b0);
or g3(Seg, p1,p2);

endmodule

module binaryToDSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g1(p1,~b3,b2,~b1,~b0);
and g2(p2,b3,~b2,~b1,b0);
and g3(p3,~b3,b2,b1,b0);
or g4(Seg,p1,p2,p3);

endmodule

module binaryToESeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g1(p1,~b3,b1,b0);
and g2(p2,~b3,b2,~b1);
and g3(p3,b3,~b2,~b1,b0);
or g4(Seg,p1,p2,p3);

endmodule

module binaryToFSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g1(p1,b1,~b3,~b2);
and g2(p2,b1,b0,~b3);
or g3(Seg,p1,p2);

endmodule

module binaryToGSeg (b3, b2, b1, b0,Seg);
input b3, b2, b1, b0;
output Seg;

and g1(p1,~b3,~b2,~b1,~b0);
and g2(p2,~b3,b2,b1,b0);
or g3(Seg,p1,p2);

endmodule

module Func_gen_and_disp (b3, b2, b1, b0,Seg);
output reg b3,b2,b1,b0;
input [6:0] Seg;

initial

begin

$monitor($time,,,"b3 = %b b2 = %b b1 = %b b0 = %b, aSeg = %b, bSeg = %b, cSeg = %b, dSeg = %b, eSeg = %b, fSeg = %b, gSeg = %b,",b3,b2,b1,b0,Seg[6],Seg[5],Seg[4],Seg[3],Seg[2],Seg[1],Seg[0]);

#10 b3 = 0; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 0; b1 = 1; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 0; b0 = 1;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 0;
#10 b3 = 0; b2 = 1; b1 = 1; b0 = 1;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 0;
#10 b3 = 1; b2 = 0; b1 = 0; b0 = 1;
#10 $finish;
end

endmodule

Thanks!

Update: I managed to get my hands on an edition of verilogger thats supports 2001 syntax, and it compiles fine. But I'm still curious as to why the old one doesnt work.

Title: Re: Help with test bench
Post by boe on Jul 6^th, 2007, 9:53am

I can't see why you should need Verilog-2001 for your last piece of code (reply #13)...
What error messages do you get?
BOE

Title: Re: Help with test bench
Post by Geoffrey_Coram on Jul 9^th, 2007, 6:30am

In several of the segments, you have intermediate results, eg binaryToBSeg has p1 and p2. Do you need to provide some sort of declaration for them?

Title: Re: Help with test bench
Post by boe on Jul 9^th, 2007, 7:36am

Geoffrey_Coram wrote on Jul 9^th, 2007, 6:30am:

In several of the segments, you have intermediate results, eg binaryToBSeg has p1 and p2. Do you need to provide some sort of declaration for them?

Cadence tools (V-XL and NCSim) do not require this. All variables that have not been specified are implicitly declared as scalar wires.
I haven't checked the Verilog standard, though...

BOE