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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Physical Verification, Extraction and Analysis >> schematic from layout? https://designers-guide.org/forum/YaBB.pl?num=1183447048 Message started by topquark on Jul 3rd, 2007, 12:17am |
Title: schematic from layout? Post by topquark on Jul 3rd, 2007, 12:17am Hey folks, I'm using cadence_ic 5.10.41.x. is there a way to generate a schematic view from layout view? In particular, I'm making metal plate caps which are not included in the library. I create the layout, simulate extracted netlist to get the cap value for the given plate dimensions. How can i associate this layout view with a "analogLib" capacitor schematic/symbol?? Any pointers? |
Title: Re: schematic from layout? Post by topquark on Jul 10th, 2007, 8:06am Hey guys, I figured it out (thanks to my boss!) You don't have to 'generate' schematic out of layout. Do the usual way. just add lvsIgnore labels when you want a certain element to be discounted in layout. In my case, i need the actual plate cap between the metal layers. So, I put analogLib capacitors in schematic and ignore them in LVS. Once, LVS is clean, extract the netlist and I get the plate cap 8-) |
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