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Design Languages >> Verilog-AMS >> verilogAMS event-OR
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Message started by Seppo on Jul 3^rd, 2007, 8:59am

Title: verilogAMS event-OR
Post by Seppo on Jul 3^rd, 2007, 8:59am

In plain verilog,

always@(b1 or b2 or b3)

will detect changes in b1, b2 or b3.

If I write

logic b1, b2, b3;

analog begin
@(b1 or b2 or b3) blah;
end

The elaborator complains that the left operand of type integer is not supported for operator "Event OR".
Writing:

analog begin
@(b1 || b2 || b3) blah;
end

works, but it not the same.

How can I get event-OR to work within an analog block?

Thanks,

Seb

Title: Re: verilogAMS event-OR
Post by boe on Jul 3^rd, 2007, 11:02am

Hi Seb,
I haven't tested this, but have you tried declaring b1, b2, b3 as wires or regs instead of integers?

BOE

Title: Re: verilogAMS event-OR
Post by Seppo on Aug 15^th, 2007, 6:03am

It turns out that digital lines are converted to integers within an analogue block, which gives raise to the problem I commented.

The bug in verilogAMS has been solved newer versions of IUS.