The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> vhdl ams in cadence https://designers-guide.org/forum/YaBB.pl?num=1183753866 Message started by piri on Jul 6th, 2007, 1:31pm

Title: vhdl ams in cadence Post by piri on Jul 6th, 2007, 1:31pm Hi, i'm trying to simulate a dc-dc buck converter with a digital control. the power cell is written in vhdl-ams, the digital control in vhdl. When i try to simulate in cadence, the simulation starts, but the power cell appears disconnected from the digital control. i try to use connect models, but the code in vhdl-ams is written so that the output of the power cell is std_logic, and correspond to the input of the digital control, so it doesn't work.... :'(

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