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Design >> RF Design >> about the control voltage of the vco in a pll
https://designers-guide.org/forum/YaBB.pl?num=1183820594

Message started by calven on Jul 7^th, 2007, 8:03am

Title: about the control voltage of the vco in a pll
Post by calven on Jul 7^th, 2007, 8:03am

hi,experts
i build a pll voltage domain model with veriloga,and it works.then i replace the vco with a real circuit of transistors while the others remains implemented by veriloga.the linear process is basiclly the same.but the waveform is very thick.in fact,if zooming out the waveform,we will find the voltage is always oscillating behind the linear process,and the control voltage does not settle to a stable value.it oscillates in a frequency much higher than the nature frequency of the pll.i do not think it is ripple because the pfd is ideal and the peak-to-peak value is close to 0.02v.and the peak value of the control voltage indeed deceases,but slowly.the pll circuit totally implemented with transistors have the same problem too.the nonlinearity of the vco causes this?give me some advice,please
best regards

Title: Re: about the control voltage of the vco in a pll
Post by calven on Jul 9^th, 2007, 3:56am

i directly connect the output of the loop filter to the varactor of the vco.is this right or not?