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Design >> Analog Design >> Cascaded Folding in Flash ADC
https://designers-guide.org/forum/YaBB.pl?num=1183861438

Message started by neoflash on Jul 7^th, 2007, 7:23pm

Title: Cascaded Folding in Flash ADC
Post by neoflash on Jul 7^th, 2007, 7:23pm

In 1997 Dec. JSSCC, Aaron Buckwald raised cascaded folding concept in high speed ADC to reduce No. comparators.

The approach there is to first folding x3 and cascade another folding x3 after it.

I do not quite follow his paper. Since folding will induce large distortion and only zero crossing is used, further folding does not have a good reference voltage. How we give 2nd stage folding x3 a good reference?