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Design >> Analog Design >> Sampling capacitor size of ADC
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Message started by neoflash on Jul 10^th, 2007, 7:35am

Title: Sampling capacitor size of ADC
Post by neoflash on Jul 10^th, 2007, 7:35am

In 2001, Abidi published a paper of "A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS".

Only 6-bit resolution is required, however, Abidi and Michael Choi added 1pF as input sampling capacitor. The thermal noise due to KT/C is only about 2mV, which is much lower than LSB quantization noise. Why they put so much capacitance there and pay the cost for high power?

thanks,
Neo

Title: Re: Sampling capacitor size of ADC
Post by loose-electron on Jul 10^th, 2007, 8:31am

in all probablity the sizing can come from a bunch of different considerations and noise is the last one.

charge injection of switches
resistance of switches and sampling time period needed
leakage rate of gates, hold time and droop characteristics
plate dielectric leakage
impedance that the hold capacitor sees

smaller C is better for fast sampling times, but the nonideal nature of the switches makes for a need to store larger amounts of charge in order to get a stable voltage.

Title: Re: Sampling capacitor size of ADC
Post by vivkr on Jul 10^th, 2007, 11:15pm

Hi Neo,

I think it is probably charge-injection and parasitic issues which are
probably responsible in this case. If you look at Fig. 5 of this paper, you
can see that the authors also use a dummy switch to prevent a jump in the
common-mode level when going from track-to-hold phase. This switch
is also useful in partially compensating for charge-injection.

There are of course other ways of designing a sample-and-hold for less power
consumption, but for this case (6-bit flash), it was probably the best way to do
it this way.

Be aware though that sometimes people may choose the cap size arbitrarily, and often
the choice is 1 pF. Not in this case I think.

However, I disagree with loose-electron when he says that noise is the last consideration for
cap sizing. If you are making high-resolution circuits, it is often the first one, but for low-res,
it may be the last.

Regards
Vivek

Title: Re: Sampling capacitor size of ADC
Post by neoflash on Jul 11^th, 2007, 4:56am

loose-electron wrote on Jul 10^th, 2007, 8:31am:

I do not agree with your point.

1. "charge injection of switches" does decrease with bigger sampling capacitor. However, to maintain same bandwidth of T/H, more sampling capacitor will incur larger switch, which increase charge injection. In short, these two effects cancel each other.

2. gate leakage of capacitor also grows linearly with capacitor size.

Title: Re: Sampling capacitor size of ADC
Post by neoflash on Jul 11^th, 2007, 4:58am

vivkr wrote on Jul 10^th, 2007, 11:15pm:

Thanks for your reply. However, i do not agree with charge injection part. Pls see my last reply. Thanks. Neo

Title: Re: Sampling capacitor size of ADC
Post by vivkr on Jul 11^th, 2007, 6:08am

neoflash wrote on Jul 11^th, 2007, 4:58am:

vivkr wrote on Jul 10^th, 2007, 11:15pm:

Thanks for your reply. However, i do not agree with charge injection part. Pls see my last reply. Thanks. Neo

Hi Neo,

What you are basically saying is that the charge-injection vs.switch Ron factor is independent of cap size. In this
you are correct. Perhaps it would be worthwhile asking the author himself. why he chose 1 pF. I can see no reason
for the large size.

Regards
Vivek

Title: Re: Sampling capacitor size of ADC
Post by joeb on Jul 18^th, 2007, 12:54am

Hi Neo,

I guess that in the proposed design they don't use dummy switches. They choose C=1pF in order to be sure that the charge injection has no effect.