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Measurements >> Phase Noise and Jitter Measurements >> PLL Noise Simulation (How to rad^2/Hz --> V^2/Hz)
https://designers-guide.org/forum/YaBB.pl?num=1184276453

Message started by eefet3 on Jul 12^th, 2007, 2:40pm

Title: PLL Noise Simulation (How to rad^2/Hz --> V^2/Hz)
Post by eefet3 on Jul 12^th, 2007, 2:40pm

I am trying to simulate a phase noise of the PLL. I have followed the instructions specified in the “Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers”.
I have used the netlist shown in LISTING 1.

My understanding is that the Noise Output of this simulation is in rad^2/Hz. How do I change it back to V^2/Hz. I would like to compare the simulated data to the measured data.

Thanks for the help,

Aleksey

Title: Re: PLL Noise Simulation (How to rad^2/Hz --> V^2/
Post by ywguo on Jul 15^th, 2007, 8:26pm

Hi, Aleksey,

Just multiply the signal power to change back to V^2/Hz as long as the amplitude noise is not large.

Yawei