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Design Languages >> Verilog-AMS >> simulate Fractional-N PLL by Cadence AMS designer
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Message started by SemiLeon on Jul 13^th, 2007, 8:10am

Title: simulate Fractional-N PLL by Cadence AMS designer
Post by SemiLeon on Jul 13^th, 2007, 8:10am

Hi, All,
I found a problem in the simulation of a Delta-Sigma fractional-N PLL by cadence AMS designer. I construct the PLL by the blocks in different forms:
(1) PFD, charge pump and loop filter: Spectre netlist
(2) VCO: verilog-A model
(3) Feedback divider and Delta-Sigma modulator: Verilog-HDL
The Delta-Sigma modulator output a divider ratio at each reference clock, and the long term average is the wanted fractional divider ratio. But in the simulation, I can't see the "averaging" effect. The PLL works as a integer-N PLL with different divider ratio at each reference clock. I also use the FFT to observe the spectrum of the output, but still hard to find out a major tone.
Is the AMS feasible for such simulation. Please give me some advise about this issue.

Thanks and Best Regards.

Leon

Title: Re: simulate Fractional-N PLL by Cadence AMS desig
Post by Marq Kole on Jul 24^th, 2007, 12:05am

In general, AMS would be perfectly suited for these kinds of systems as you have nearly all the behavior you need without the simulation cost of a transistor-level model.

Although I'm no expert on these things, if the VCO (= PLL output) reacts that quickly to changes as you describe, it sounds like the loop filter is not doing its job. The rate of change in the divider should be higher than the loop filter bandwidth.