The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> Issues with Virtuoso AMS
https://designers-guide.org/forum/YaBB.pl?num=1184442782

Message started by leena2k6 on Jul 14^th, 2007, 12:53pm

Title: Issues with Virtuoso AMS
Post by leena2k6 on Jul 14^th, 2007, 12:53pm

Hi,

I have recently started to develop AMS environment(Cadence Virtuoso AMS) at chip level.
The testbench components are System Verilog and the design is mixed verilog + vhdl.

While running verilog -irun ...command, i see some issues in ncelab. The error is something like -
Hierarical component lookup failure testbench.top.......cfash0.ftop.IFLH

FYI, the same pattern runs fine when run without ams options i.e without giving -propspath option in the verilog run command.
Also the testbench is SV, top, cfash0 is verilog code, ftop is a vhdl code whereas IFLH is verilog.

The cflash0, ftop, IFLH are all digital blocks.

Any clues why do i see this issue?

Thanks,
Leena

Title: Re: Issues with Virtuoso AMS
Post by Daniel Liu on Aug 7^th, 2007, 2:41pm

Hi Leena,

My name is Daniel Liu, AMS PE from Cadence. I got forward for your issues. I have good news for you. Ramkumar has been working with us and we are sending his an ER with this fix.

Please check with him a little bit latter.

Thanks,
Daniel