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Design >> Mixed-Signal Design >> series caps for good matching
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Message started by vivkr on Jul 17^th, 2007, 2:36am

Title: series caps for good matching
Post by vivkr on Jul 17^th, 2007, 2:36am

Hi,

When realizing a successive approximation type of converter, one often uses a capacitive DAC.
The limitation here is usually mismatch, particularly due to the large variations on the smallest
caps which are 2^N times smaller than the largest ones, and the standard method is to choose a large
enough unit element cap, but this gives too much capacitance => more power.

From time to time, people talk of using multiple unit caps in series to realize the smaller caps in the C-DAC.
For instance, an 8-bit C-DAC may have 16 unit caps in parallel for the largest element and 16 unit caps in series
for the smallest one (to exaggerate, as this would still not be a good solution).

How does one control the intermediate high-Z nodes now? There will be several problems including charge-deposition
during the ion etch process on these plates. If one were to tie a reverse-biased diode to these plates, then the leakeage current
of these would wreak havoc at these high-Z nodes.

Is there a way around?

Thanks
Vivek

Title: Re: series caps for good matching
Post by ACWWong on Jul 17^th, 2007, 3:48am

With regards to MIM caps, its often the case that the bottom plate must contact up to the level of metal above (the same level as the contact for the top plate) before contacting down the metal stack. This avoids charge build up concerns during processing and so should negate the need for tiedown diode.

Title: Re: series caps for good matching
Post by vivkr on Jul 17^th, 2007, 5:59am

ACWWong wrote on Jul 17^th, 2007, 3:48am:

Hi ACWWong,

Could you please explain a bit more? You say that there is no problem if the bottom plate is contacted up to the same level of metal as the
top plate. But it is contacted to a different piece of metal. Does this not result in charge accumulation still?

Also, are there any other issues except the ion etching one?

Thanks very much.
Vivek

Title: Re: series caps for good matching
Post by ACWWong on Jul 17^th, 2007, 6:54am

try this link...

http://ieeexplore.ieee.org/iel5/9162/29077/01309925.pdf

figure 4. shows how i routinely contact MIMs to avoid plasma enduced damage... during processing, both plates are left to float together, thus reducing the stress on the dielectric.

Although this diagram goes for belt & braces approach with addition antenna diodes, for critical nets depending on MIM type/sizes it is also possible remove the need for diffusion contact (antenna diode), but the best source for advice on this would be your foundry.

hope this helps..

Also i agree 16 series caps is over the top, but do routinely use 2.

aw

Title: Re: series caps for good matching
Post by RobG on Jul 17^th, 2007, 3:15pm

Vivek - I have used a "splitting capacitor" between two five bit cap dacs to create a 10 bit cap dac for a sar. I think bottom plate capacitance will prevent you from doing more than one splitter cap because you need the bottom plate parasitic to be on the comparator input to prevent non-linearities.

I don't remember the details, but handling the high Z node was easy. I think I just connected both sides of the splitting capacitor to the same potential when sampling the input. It worked fine.

rg

Title: Re: series caps for good matching
Post by RobG on Jul 17^th, 2007, 3:37pm

Vivek --
I just remembered a paper from 2006 ISSCC by Chen and Broderson from Berkeley (p574 of the proceedings). They used a cap ladder network (similar to an R-2R network). They intentionally made the ratios less than two so that the bottom plate wouldn't create missing codes, and then used calibration to figure out what the actual ratios should be. I don't see how they controlled the floating node, but you could easily switch it to Vcm during the sampling phase. I don' tknow if any follow-up work has been done.

But... if you are going to calibrate anyway, obtaining matching isn't the primary concern.

rg

Title: Re: series caps for good matching
Post by vivkr on Jul 17^th, 2007, 11:17pm

Hi ACWWong,

I am afraid I have no way of accessing this paper as my subscription is only to JSSC. Is there
some other place where I may see the same system that you desribe? I would be very glad to
have it for reference. I don't know for sure if I will have MIM caps or only poly-poly,
but it would be good to have a potential solution.

Hi Rob,

I have seen the paper by Chen and Brodersen but as you pointed out, they show no technique
for setting the intermediate nodes. I think switching them to the common-mode during sampling
may not work that well for 2 reasons:

1. The additional junction capacitance at the nodes will be a problem as will the leakage from these
2. The overall sampling capacitance will increase quite a lot. Chen keeps those caps in series while sampling
so as to reduce overall capacitance as much as possible.

I am not using calibration, but trying to use the series caps to improve matching.

Thanks & Regards
Vivek

Title: Re: series caps for good matching
Post by RobG on Jul 18^th, 2007, 7:32am

vivkr wrote on Jul 17^th, 2007, 11:17pm:

1. The additional junction capacitance at the nodes will be a problem as will the leakage from these
2. The overall sampling capacitance will increase quite a lot. Chen keeps those caps in series while sampling
so as to reduce overall capacitance as much as possible.

I don't think those will be big issues. Use a small switch. You don't have to bring the node to precisely the common mode point - just get them close. If you are going to put a junction on that node to keep them safe during processing it may as well be active.

I am more worried about the bottom plate parasitic... Perhaps you could put a shield so it is always connected to the comparator input.

rg

Title: Re: series caps for good matching
Post by Terence on Jul 30^th, 2007, 10:30pm

I think both balanced interconnection suggested by ACWWong and junction diode are both required to avoid MiM damage during plasma process. The junction diode can not be neglected because the metal area for top & bottom plate is not easy to be identical, which induces potential difference on MiM.

Title: Re: series caps for good matching
Post by fran2k5 on Aug 3^rd, 2007, 2:50am

Hi,

in the case you use poly-poly caps, in order to avoid charge build up you could use the same technique used for floating gate transistors.
You could put on the poly of the high Z nodes a via that does not contact any actual metal. Since during processing all the chip surface is covered by metal, the two plates will be at the same potential.

Regards,

fran2k5