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Design >> Analog Design >> Power Noise in Analog Chips
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Message started by neoflash on Jul 17^th, 2007, 8:02am

Title: Power Noise in Analog Chips
Post by neoflash on Jul 17^th, 2007, 8:02am

I'm designing high speed clocking chips. As we know, every kind of PLL has certain kind of vulnerability, more or less, to supply noise.

If customer clearly defines the possible noise amplitude and frequency on the chips, we could derive whether our chips could tolerate it.

However, it seems that there is no such kind of specifications. What is the rule of thumb?

Title: Re: Power Noise in Analog Chips
Post by ywguo on Aug 9^th, 2007, 2:06am

Hi,

Sure the PLL is vulnerable to the supply noise. Sure the suppily is very noisy if it connects to digital cells which toggle frequently. However, we separate the PLL supply from the digital supply normally. We try to give a clean supply to the PLL.

By the way, it is difficult to define the possible noise amplitude and frequency on the chips when you design the PLL. That is because the digital design is often huge, the design cycle is not finish.

Yawei