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Design Languages >> Verilog-AMS >> Whatis Pout & Pin in VerilogA model for Freq.divid
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Message started by savithru on Jul 18^th, 2007, 12:34am

Title: Whatis Pout & Pin in VerilogA model for Freq.divid
Post by savithru on Jul 18^th, 2007, 12:34am

hi

I am using the verilogA model for the frequency divider given in the pdf "Hidden State in SpectreRF" by Ken Kundert,
Designer’s Guide Consulting, Inc.

You have used the following

module divideByN(pout, nout, pin, nin);

Here you defune the module by the name divideByN with pout, nout, pin, nin as ports.

But I could not undestand what are these Pout and Pin ports.

kindly reply.

Regars
SavithRu

Title: Re: Whatis Pout & Pin in VerilogA model for Freq.d
Post by Ken Kundert on Jul 18^th, 2007, 1:13am

The input signal is measured between pin and nin (the positive and negative inputs). The output signal is forced between pout and nout (the positive and negative outputs). In most cases, nin and nout are connected to ground. Then pin becomes the input and pout becomes the output.

-Ken

Title: Re: Whatis Pout & Pin in VerilogA model for Freq.d
Post by savithru on Jul 18^th, 2007, 8:13pm

Hello sir,

Thank you very much for your reply..

How ever my divider is not working.. output is alwaus at zero.

Do I need to change any thing in the code.

In the code you have taken N=2 ( Divide by 2?). I am going ahead with the same.

I have changed the vdd power supply to my vdd=1.5v.

I did not touched any of the remaining code. I created the symbol, and trying to simulate in the spectreRF. But my output is always at zero..

Kindly guide me, where I am wromng?

Pls reply.

Thanks & regards
SavithRu

Title: Re: Whatis Pout & Pin in VerilogA model for Freq.d
Post by Ken Kundert on Jul 18^th, 2007, 8:20pm

There are any number of things that could be wrong. If you would like help, you should post a simple test case (netlist and vlog-a files) that demonstrates the problem.

-Ken

Title: Re: Whatis Pout & Pin in VerilogA model for Freq.d
Post by savithru on Jul 18^th, 2007, 8:36pm

Hello sir, Thanks for your quick reply.

I am not using any test module as given by you in the pdf.

I' ve simply crerated the symbol and put in to schematcic editor and simulating.

I am attachning the test schematic.. I thought this works..

Pls reply where I am wrong.

Thanks & regards
SavithRu

Title: Re: Whatis Pout & Pin in VerilogA model for Freq.d
Post by savithru on Jul 18^th, 2007, 8:43pm

Sorry.. I missed the test sch.

Title: Re: Whatis Pout & Pin in VerilogA model for Freq.d
Post by Geoffrey_Coram on Jul 19^th, 2007, 4:47am

Your problem is that your input source V0 doesn't ever get high enough: it has v2=1.5, but the threshold of the divider is 2.5, per these lines from the code:

parameter real vdd=5, vss=0; // defines output high and low levels
parameter real thresh=(vdd+vss)/2; // input threshold is at midpoint

I also thought it was strange that V0 has "v1:0.0" (with a colon ":") but "v2=1.5" (with equals "=") ...