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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> modelling nfet and pfet behavioural model verilogA https://designers-guide.org/forum/YaBB.pl?num=1184796475 Message started by nishanis on Jul 18th, 2007, 3:07pm |
Title: modelling nfet and pfet behavioural model verilogA Post by nishanis on Jul 18th, 2007, 3:07pm Hello, I am trying to write a verilog-a behavioral model for pfet and nfet, i.e. using them as switches. analog begin if (analysis("static")) begin Rch = Roff ; end else begin if (V(G) >=Vth) Rch = Ron ; else Rch = Roff ; end; I(S, D) <+ V(S, D) / transition(Rch,0,tr,tf); end endmodule The model works fine. But when i use both pfet and nfet models to build an inverter i just get 0 at output. I think i need voltage as output. SO i tried V(S, D) <+ I(S, D) * transition(Rch,0,tr,tf); But this gives segmentation fault in spectre. Can anybody tell some changes in the model where i can model voltages? Also, is there a standard model for nfet or pfet to operate them as switches which can be used to build logic gates. Waiting for reply. :) |
Title: Re: modelling nfet and pfet behavioural model veri Post by Ken Kundert on Jul 18th, 2007, 7:33pm Try mos0, a built-in primitive in Spectre. |
Title: Re: modelling nfet and pfet behavioural model veri Post by Ken Kundert on Jul 18th, 2007, 7:35pm Alternatively, you can use the logic expression capability in Vlog-A to build true behavioral models of the gates. -Ken |
Title: Re: modelling nfet and pfet behavioural model veri Post by Geoffrey_Coram on Jul 19th, 2007, 10:25am nishanis wrote on Jul 18th, 2007, 3:07pm:
Segmentation fault? Cool. Are you running a current version of the simulator so you can open a support request? When you used the curent formulation, did you remember to invert the sense of the gate voltage? I'd also have used V(G,S) rather than just V(G). |
Title: Re: modelling nfet and pfet behavioural model veri Post by nishanis on Jul 20th, 2007, 10:38am Hello Ken, Thanks for replying. Can you explain about the logic expression capability in Vlog-a. are you referring to model writer to get the behavioral model? Thanks |
Title: Re: modelling nfet and pfet behavioural model veri Post by nishanis on Jul 20th, 2007, 10:40am Hello Geoffrey_Coram, I tried your solution, its still giving the same segmentation fault. I tried doing this also, but same error analog begin if (analysis("static")) begin Rch = Roff ; end else begin if (V(G,S) < Vth) Rch = Ron ; else Rch = Roff ; end a = transition(Rch,0,tr,tf); V(S,D) <+ I(S,D) * a; end endmodule Hope to get further help from you. thanks :) |
Title: Re: modelling nfet and pfet behavioural model veri Post by Ken Kundert on Jul 20th, 2007, 12:56pm Go to the Verilog-AMS page and download the basic inverter. This is the starting point. Add more inputs and calculate the output using simple logical expressions (&&, ||, !, etc.). -Ken |
Title: Re: modelling nfet and pfet behavioural model veri Post by nishanis on Jul 20th, 2007, 2:34pm Hello ken, I have done one set of simulation using those codes to which you are referring. But what i am trying to achieve is i have two models (pfet and nfet) so if anybody designs gates like, AOI222, or AO or any other, i wouldn't have to model another code. spectre would use those fet models and would act as switch and implement the functioning. I got away with segmentation fault, using code below. But at output i am getting 1.8v straight line. its not switching when vth drops. Its always at 1.8v when i/p is at 1.8v and 0 v when i/p as it 0v. analog begin @(cross (V(control)- vth, 0, slack, control.potential.abstol)) begin if (V(control) >= vth ) rout = roff; else rout = ron; end a = transition(rout,0,100p,100p); V(vin,vout) <+ I(vin,vout) * a; end endmodule |
Title: Re: modelling nfet and pfet behavioural model veri Post by sheldon on Jul 25th, 2007, 9:31pm Nishanis, In this case it might be easier to use the sw_no from the bmslib to create the n-channel and p-channel device models. The model formulation of the sw_no does not use the "if" function. This approach works well for switching regulators[synchronous buck converters]. One point to consider is the on resistance of the switch, it needs to be relatively high to minimize shoot-through current. Best Regards, Sheldon |
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