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Design >> Analog Design >> 65 nm layout issues, WELL proximity etc.. Help me
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Message started by babya on Jul 19^th, 2007, 7:47am

Title: 65 nm layout issues, WELL proximity etc.. Help me
Post by babya on Jul 19^th, 2007, 7:47am

Hi all,

Will anybody please help me with "Well proximity error" ? What exactly is this? what is it's impact on device performance? how can it be taken care in layouts?

can anybody give me an idea of similar issues in 90-65nm processes?

Thanks in advance,

Title: Re: 65 nm layout issues, WELL proximity etc.. Help
Post by didac on Jul 19^th, 2007, 8:47am

Hi babya,
Months ago doing a little google search I found this interesting paper:http://www.solidodesign.com/publications/1_drennan_cicc06_v3f.pdf, it explains very clear the new issues due to sub 100nm technologies. As it is stated well proximity causes differences on threshold voltage and creates also asymmetric behaviour between S/D.
Hope it helps,