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Modeling >> Semiconductor Devices >> Max. Vds for 3.3V pMOS in 0.18um CMOS process
https://designers-guide.org/forum/YaBB.pl?num=1185168259

Message started by Terence on Jul 22^nd, 2007, 10:24pm

Title: Max. Vds for 3.3V pMOS in 0.18um CMOS process
Post by Terence on Jul 22^nd, 2007, 10:24pm

Hi,

I would like to operate 3.3V pMOS of generic 0.18um CMOS process in the following conditions.
Bias: Vds=5V ; Vgs=3.3V ; Vsb=0 ; Vb=0
Size: W/L = 20/0.3

Is there any realibility or punch-through issue?

Thanks.
Terence

Title: Re: Max. Vds for 3.3V pMOS in 0.18um CMOS process
Post by Marq Kole on Jul 26^th, 2007, 7:33am

Of course there are reliability issues: you're using the device outside it normal operating conditions. The process design guidelines should be able to tell you what the maximal Vds is at which most devices will break down.

Consider also that you are putting a field of 5V/0.3um = 1.67e+07 V/m across the channel. You might expect some HCI issues, I would say. I presume this is the minimum length for a 3v3 compliant PMOS device?

What could be worse is that the model parameters are not valid in this operating region - that really depends on the characterization procedures for the given device. Again, the documentation of the process should be able to give you the details.

Title: Re: Max. Vds for 3.3V pMOS in 0.18um CMOS process
Post by krishnap on Aug 1^st, 2007, 11:14pm

usually foundry datasheet will have the maximum volage that can be applied for the device.
so that the device will operate within the safe reliability limits.
Also the time duration for which the device is connected to the higher voltage. For shorter time it is ok.
Another way is to have devices in series so that Vds is distributed, when higher volatge need to be applied.