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Design Languages >> Verilog-AMS >> counter-64
https://designers-guide.org/forum/YaBB.pl?num=1185357684

Message started by kamath on Jul 25^th, 2007, 3:01am

Title: counter-64
Post by kamath on Jul 25^th, 2007, 3:01am

module counter(in,out,clock);
input in,clock;
output [5:0]out;
reg [5:0]out;
initial out=0;

always begin
@(posedge clock)
if( (out<63) && in);
out= out+1;
if(~(out==0) && ~in);
out=out-1;
end
endmodule

i want to design 64 bit up-down counter,but this prog did not give any result,plz help me.
i am a newbie so forgive if any silly mistakes.

Title: Re: counter-64
Post by boe on Jul 26^th, 2007, 4:59am

Hi kamath,
you need to put the if statements in a begin-end block.
In your code, the @-event only affects the first if statement.

BOE