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Design Languages >> Verilog-AMS >> Latch using switch model of mosfets in verilog-a!!
https://designers-guide.org/forum/YaBB.pl?num=1185399500

Message started by nishanis on Jul 25^th, 2007, 2:38pm

Title: Latch using switch model of mosfets in verilog-a!!
Post by nishanis on Jul 25^th, 2007, 2:38pm

Hello,
I have a switch model for nfet and pfet. All combinational gates work fine with those models. I was modeling a latch with the that model. But it wont store a value. So i added capacitor between gate and source and capacitor between source and drain. Still the result is always same it 1.8v irrespective of the input.
I(G,S) <+ c1 * ddt(V(G,S));
if (V(G) >= 0.9) Rch = Roff ;
else Rch = Ron ;
I(S,D) <+ c1 * ddt(V(S,D));
a = transition(Rch,0,0,0);
V(S,D) <+ I(S,D) * a;
This is for nfet. Can you suggest why is it not working? the c1 value i am using is 1fF as my ron =100 ohms.
hoping to get the solution to work with this.
thanks

Title: Re: Latch using switch model of mosfets in verilog
Post by Marq Kole on Jul 26^th, 2007, 12:00am

Apart from the V(G) in the if statement where I would expect a V(G,S) given that the rest of the code is relative to the S terminal as well, I don't see anything obviously wrong with this model. (In the absence of the rest of the model code).

Do you need the transition statement for the channel resistance?

How did you model the latch?

Title: Re: Latch using switch model of mosfets in verilog
Post by nishanis on Jul 26^th, 2007, 11:10am

hey,
well what i am doing is, i have a generic model for pfet and nfet. THe latch is a DLATCH, i have the schematic and i am placing my model in place of actual pfet and nfets. It is working for all types of gates. But failing for latch. So i think i need to store that value somehow. THe code that is there seems logically correct, and i did the V(G,S) its not making any difference. So can you provide any other solution.
Thanks a lot!!