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Design Languages >> Verilog-AMS >> Skipping first few clock cycles for cross statemen
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Message started by sylak on Jul 25^th, 2007, 3:07pm

Title: Skipping first few clock cycles for cross statemen
Post by sylak on Jul 25^th, 2007, 3:07pm

I am writing a code for a counter and am using @cross statement to begin my count. But I wasnt to skip first few clcok cycles before I start my counter. Is there a way to do this trick?

Title: Re: Skipping first few clock cycles for cross stat
Post by kamath on Jul 25^th, 2007, 10:52pm

hai,
y dont u include a delay buffer for the clock so that the number of clocks to be skipped can be calculated and so much delay given...
hope this works,ne other solution do tell me.....
bye

Title: Re: Skipping first few clock cycles for cross stat
Post by Marq Kole on Jul 26^th, 2007, 12:16am

Use an integer variable active that you set/unset based on any condition you require, and have the counter only count when active is set.

Code:

parameter real tstart = 1u from [0:inf);
integer active;

analog begin
if ($abstime > tstart)
active = 1;

@(cross(V(in)-0.5, +1))
if (active)
count = count + 1;

end

The code that sets active can be anything, also a number of counts made, a signal on a terminal, etc.

Title: Re: Skipping first few clock cycles for cross stat
Post by sylak on Jul 26^th, 2007, 1:37pm

Thanks Marq..That helped