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Design Languages >> Verilog-AMS >> mux-64:1
https://designers-guide.org/forum/YaBB.pl?num=1185460850

Message started by kamath on Jul 26^th, 2007, 7:40am

Title: mux-64:1
Post by kamath on Jul 26^th, 2007, 7:40am

hi,
i need to code a 64:1 mux in behavioral level.If i use a case then there would be 64 input and it will be a bulky code.incase a use 4:1(mux code) and instantiate then would there be anyy delay problem.
what would be the efficient way to do this..

thanx

Title: Re: mux-64:1
Post by boe on Jul 27^th, 2007, 1:57am

Hi kamath,
Did you try a bus signal for your inputs?
Hope this helps...
BOE

Title: Re: mux-64:1
Post by boe on Jul 27^th, 2007, 9:12am

Something along the lines of

Code:

`include "constants.vams"
`include "disciplines.vams"

module test ( inp, outp, ctrl );
input [63:0] inp;
input [ 5:0] ctrl;
output outp;

electrical [63:0] inp;
electrical outp;

analog begin
V(outp) <+ V(inp[ctrl]);
end
endmodule

It compiles on my system, but I haven't checked what it does...
BOE

Title: Re: mux-64:1
Post by Bill Toole on Feb 9^th, 2008, 12:10pm

Hi

I would like to implement a mux very similar to the code boe suggested for a simulation test bench where i want to set one input for the entire simulation. So instead of using a control signal i would like to use an integer parameter to select the input of the mux. Here is my code

`include "constants.vams"
`include "disciplines.vams"

module 64bit_mux(inp, outp);
input [63:0] inp;
output outp;

electrical [63:0] inp;
electrical outp;

parameter integer N=0 from [0:63];

analog begin
V(outp) <+ V(inp[N]);
end
endmodule

However, it will not compile and i get the error message

Error found by spectre during SpectreHDL compile.
"/64bit_mux/veriloga/veriloga.va",
line 16: "V(outp) <+ V(inp[N])<<--? ;"
"/64bit_mux/veriloga/veriloga.va",
line 16: Error: The index used to access bits of analog signal vector
`inp' is not a constant, constant expression, genvar variable or a
genvar-constant expression. To avoid this problem, ensure that the
indexes used to access the bits of analog signal vectors are constants,
constant expressions, genvar variables or genvar-constant expressions.

I tried using a genvar variable but no luck. Sugestions?

Bill

BTW, I tried the same code as BOE but get the same error message as above

Title: Re: mux-64:1
Post by ACWWong on Feb 9^th, 2008, 5:51pm

hi bill,

try using an intermediate variable, so this will work:

`include "constants.vams"
`include "disciplines.vams"

module 64bit_mux(inp, outp);
input [63:0] inp;
output outp;

electrical [63:0] inp;
electrical outp;

integer in_var[63:0];
integer k;
real out_var;

parameter integer N=0 from [0:63];

analog begin

generate k (0,63) begin
in_var[k] = V(inp[k]);
end

out_var = in_var[N];

V(outp) = out_var;
end
endmodule

cheers
aw

Title: Re: mux-64:1
Post by Bill Toole on Feb 12^th, 2008, 5:02am

Thanks AW, that did the trick

Bill