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Design Languages >> Verilog-AMS >> mux-in-verilog-ams
https://designers-guide.org/forum/YaBB.pl?num=1185549462

Message started by kamath on Jul 27^th, 2007, 8:17am

Title: mux-in-verilog-ams
Post by kamath on Jul 27^th, 2007, 8:17am

hai,
i have tried this code in verilog-ams...

i get glitches sometimes in the output waveform,plz sugest some solution.Also the vtrans in the model has no use,also tell me more abt the vh,vl ie vhigh and vlow....

`include "constants.vams"
`include "disciplines.vams"

module mux(p1,p2,p3,p4,s1,s2,out);
parameter real vh=0.75;
parameter real vl=0.75;
parameter real vtrans=0;
output out;
input p1,p2,p3,p4,s1,s2;
electrical p1,p2,p3,p4,s1,s2,out;
analog begin
if ((V(s2)-vtrans) <= vl && (V(s1)-vtrans) >= vl)
V(out)<+V(p1);
if ((V(s2)-vtrans)<=vl && (V(s1)-vtrans)>=vh)
V(out)<+V(p2);
if ((V(s2)-vtrans)>=vh && (V(s1)-vtrans)<=vl)
V(out)<+V(p2);
if ((V(s2)-vtrans)>=vh && (V(s1)-vtrans)>=vh)
V(out)<+V(p3);
end
endmodule

Title: Re: mux-in-verilog-ams
Post by boe on Jul 27^th, 2007, 9:36am

Hi kamath,
Some comments after a quick look on your code:
1. Contribution statements (using "<+") add up if more than one is active at the same time. For your parameter set (vl=vh), this is the case for V(sX)-vtrans = vl. I suggest you use "if then else"...
2. It should be (V(s1)-vtrans) <= vl in the first if statement.
3. I suppose vtrans is a hysteresis? Then you need different signs for high and low.
4. You could try something like this: http://www.designers-guide.org/Forum/YaBB.pl?num=1184970208/0#0

BOE