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Design Languages >> Verilog-AMS >> count
https://designers-guide.org/forum/YaBB.pl?num=1185722035

Message started by kamath on Jul 29^th, 2007, 8:13am

Title: count
Post by kamath on Jul 29^th, 2007, 8:13am

could nebody explain the use of pulse_shape and pulse_clock and the general working of the prog

`include "disciplines.vams"
`include "constants.vams"
`define N_Counts 5
`define N_offset 0
// Counter counts N_Counts and provides a pulse every N_offset counts
// Pulse is width of clock
module Counter1(rst,clk,out);
input rst,clk;
output out;
voltage rst,out,clk;

parameter real max_out = 1.2;
parameter real edge_time = 0;

real vout,clk_pulse;
integer count,clk_shape;

analog begin
@(initial_step) begin
count = -1;
end

@(cross(V(rst)-0.6,+1)) begin
count = -1;
end

@(cross(V(clk)-0.6,+1)) begin
count = count + 1;
clk_shape = 1;
if (count > (`N_Counts-1))
count = 0;

clk_pulse = (count == `N_offset) ? max_out : 0;
end

@(cross(V(clk)-0.6,-1)) begin
clk_shape = 0;
end

V(out) <+ transition(clk_pulse*clk_shape,edge_time,edge_time);
end
endmodule

Title: Re: count
Post by boe on Jul 30^th, 2007, 4:23am

Hi kamath,
count cycles between 0 and `N_Counts-1 on rising edges of V(clk):

Code:

@(cross(V(clk)-0.6,+1)) begin
count = count + 1;
if (count > (`N_Counts-1))
count = 0;
end

clk_shape is 1 while V(clk) > 0.6 (set to 1 at rising edges of clk [@(cross(V(clk)-0.6,+1))] and back to 0 at the falling edges [@(cross(V(clk)-0.6,-1))]...).
And clk_pulse goes to max_out when count == `N_offset, so you get a pulse (with length = high phase of clk) to max_out every `N_Counts clcoks.
BOE