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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Model for a clocked comp compatible with Spectre https://designers-guide.org/forum/YaBB.pl?num=1185793008 Message started by Gabriel on Jul 30th, 2007, 3:56am |
Title: Model for a clocked comp compatible with Spectre Post by Gabriel on Jul 30th, 2007, 3:56am Hi, I am new to Verilog-A modeling. I've been trying to write a model for a clocked comparator, but it seems that my code has a hidden state. `include "discipline.h" `include "constants.h" module comp (inp, inm, set, en, out); input en, set, inp, inm; output out; electrical inp, inm, en, out, set; parameter real vlogic_high=5,vlogic_low=0; parameter real vtrans=(vlogic_high+vlogic_low)/2; parameter real tdel = 2u from [0:inf); parameter real trise = 1u from (0:inf); parameter real tfall = 1u from (0:inf); real out_val; analog begin @(cross( V(en)-vtrans,+1 )) out_val = (V(inp) > V(inm)) ? vlogic_high : vlogic_low; V(out) <+ transition( out_val, tdel, trise, tfall); end endmodule Can anybody give me some help in removing this hidden state from my model? Many thanks, Gabriel |
Title: Re: Model for a clocked comp compatible with Spect Post by Frank Wiedmann on Jul 30th, 2007, 7:29am Take a look at http://www.designers-guide.org/Analysis/hidden-state.pdf. |
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