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Design Languages >> Verilog-AMS >> is there an equivalent in VerilogA for wait statem
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Message started by sylak on Jul 30^th, 2007, 4:02pm

Title: is there an equivalent in VerilogA for wait statem
Post by sylak on Jul 30^th, 2007, 4:02pm

I am trying to replace some VHDL-AMS code with VerilogA, Here is a piece of code I want to replace... I cant think of any operation that can replace "wait" (in VHDL) in Verilog-AMS..

loop
wait for quarPeriod;
state_90 := not state_90;
CLK90 <= state_90 and powerdown;
end loop

Title: Re: is there an equivalent in VerilogA for wait st
Post by Ken Kundert on Jul 30^th, 2007, 5:16pm

use

Code:

@(timer(...)) begin
...
end

-Ken

Title: Re: is there an equivalent in VerilogA for wait st
Post by sylak on Jul 30^th, 2007, 6:37pm

Ken,

Thank you for the reply

I am generating a (oscillating) clock signal using the loop signals which inverts the CLK90 everytime.. Can I use a "forever" statment to substitute for the 'loop' statement? More importantly can it be used inside an "analog begin"

What is the syntax for such a statement?

Title: Re: is there an equivalent in VerilogA for wait st
Post by Ken Kundert on Jul 30^th, 2007, 7:05pm

Take a look at the fixed frequency oscillator model in http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf.

You don't need any kind of loop statement at all. That is not the way the analog section works. It is run on every time step. So you instead you use @(timer(...)) to avoid executing statements that update the state of the model except at the desired points in time. So you would using something like ...

Code:

@(timer(next)) begin
state = !state;
next = next + period/2;
end
V(out) <+ transition(state);

-Ken