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Modeling >> Behavioral Models >> voltage dependent capacitor model
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Message started by vivkr on Jul 31^st, 2007, 4:12am

Title: voltage dependent capacitor model
Post by vivkr on Jul 31^st, 2007, 4:12am

Hi,

I am trying to write a VerilogA model for a voltage dependent cap where

C = f(V(cp,cn)) where cp and cn are the controlling terminals, and C itself is connected
between 2 other terminals p & n.

I always run into errors with the compiler which refuses to allow multiplication of a signal-based
quantity with a ddt operator, or use of a ddt operator on the product of 2 signals.

Is there a good way of making such a model. Incidentally, I am aware that modelling a cap like this is
perilous, but for my testbench, it would work.

Thanks
Vivek

Title: Re: voltage dependent capacitor model
Post by boe on Jul 31^st, 2007, 5:32am

Hi Vivek,
There are a few restrictions on using the ddt operator, try using an intermediate signal....
BOE

Title: Re: voltage dependent capacitor model
Post by vivkr on Jul 31^st, 2007, 5:42am

Hi Boe,

Could you please elaborate? I did try to use an intermediate signal by creating a node and then trying to split
the task of the voltage-dep cap by creating a voltage dependent function on this node and trying to use this
to realize the cap, but it didn't work either. Seems like any reference to another signal, no matter how implicit,
is banned, when used alongside ddt.

Regards
Vivek

Title: Re: voltage dependent capacitor model
Post by boe on Jul 31^st, 2007, 5:53am

Hi Vivek,
I usually use something like

Code:

electrical sig, ddt_sig;
V(ddt_sig) <+ ddt(V(sig));

Then I work with the signals V(sig) and V(ddt_sig)...
And the ananlog operators (ddt etc) are not allowed in (dynamic) conditional statements, loops etc. (at least in my simulator)...
Hope this helps. If not, please give a piece of code...
BOE

Title: Re: voltage dependent capacitor model
Post by vivkr on Jul 31^st, 2007, 6:55am

Hi boe,

I tried the intermediate node trick, and it does work.

Thanks a lot.

Vivek

Title: Re: voltage dependent capacitor model
Post by Ken Kundert on Jul 31^st, 2007, 10:58am

The techniques you are using are inappropriate and will likely result in incorrect results and convergence problems.

The first problem is in the way you formulate your capacitor. When you calculate C as a nonlinear function of voltage, and then try to convert C to current, you end up with the wrong capacitance and charge conservation problems. You should instead compute the charge analytically, and then differentiate it with ddt() to compute current. This eliminates the accuracy problem. It also eliminates the problem you have having with the simulator, that leads you to your second problem.

The second problem is that you are using an internal node, which also results in two problems. First, an internal node is kind of expensive. Second, it has the wrong tolerances. You declare the internal node to be electrical, but it is not. As a result, you are using the wrong tolerances for that signal, which can result in convergence problems if they are too tight or accuracy problems if they are too loose.

I recommend that you follow the guidance provided in "Modeling Varactors", http://www.designers-guide.org/Modeling/varactors.pdf.

-Ken

Title: Re: voltage dependent capacitor model
Post by safwatonline on Feb 16^th, 2008, 6:40am

Hi Ken,
i saw your reply to the topic and i have a question, does these problems happen when the cap voltage is controlled by the same voltage on it, (i.e. in the case mentioned by vivkr where he have separate ports for controlling the cap, he shouldn't see that problems)
or it happens even in that case.
regards,
Safwat

Title: Re: voltage dependent capacitor model
Post by Ken Kundert on Feb 17^th, 2008, 12:49am

If the controlling terminals are distinct from the capacitors terminals you still need to be careful or you will get nonphysical results.

Imagine you had
i = C(x)*dv/dt
and C(x) was such that for some value of x, say x₁, C(x₁)=1 and for another value of x, say x₀, C(x₀)=0. Now set x = x₁ and connect the capacitor to a 1v DC source such that v=1 and dv/dt=0. The capacitor is now holding 1 Coulomb of charge. Now change x to x₀. Now the charge on the capacitor must be 0 because C is 0, but because dv/dt=0 no current actually left the capacitor. Charge is not conserved.

-Ken

Title: Re: voltage dependent capacitor model
Post by safwatonline on Feb 17^th, 2008, 1:18am

Ken Kundert wrote on Feb 17^th, 2008, 12:49am:

Thanks for the help Ken, i agree with you however what if i put I=dq/dt and q=C(x)*V
then i should get I=C*(dV/dt)+V*(dC/dt)
so while the first term will not introduce current, the second term will produce current discharging the charge, is that correct?
BTW lets say i implemented this model how to verify it, since i don't have access to charges

Title: Re: voltage dependent capacitor model
Post by Ken Kundert on Feb 17^th, 2008, 2:03pm

Yes, you are correct, so your approach is fine as long as the capacitor is linear. However, I am surprised by your comment that you don't have access to the charge. For a linear capacitor charge is simply equal to the capacitance times the voltage.

-Ken

Title: Re: voltage dependent capacitor model
Post by safwatonline on Feb 18^th, 2008, 9:05am

Ken Kundert wrote on Feb 17^th, 2008, 2:03pm:

Thanks ken for your help,
i think i got it now, so let me say what i understood, if C is not function of V ( even if C is changing on its own) then q=CV and i can use I=dq/dt without causing error
and if C is a function of V then q =! CV but q=∫₀^vCdV, so i need to calculate the q analytically to maintain the charge conservation and i cannot use here q=CV as this is a linear equation which doesn't satisfy the C(V) condition.

thanks a lot Ken.
regards,
Safwat

Title: Re: voltage dependent capacitor model
Post by imd1 on Feb 18^th, 2008, 9:33am

safwatonline wrote on Feb 18^th, 2008, 9:05am:

Ken Kundert wrote on Feb 17^th, 2008, 2:03pm:

The integral q=∫₀^vCdV is a path integral, have you any method for evaluating it ? I'd like to build a macro-model of a non-linear capacitance where q=C(v)*v and I was wondering if applying a sine voltage and integrating the current over a cycle would do the trick (of extracting the q=C(v)*v curve).

BTW, anyone knows how dielectric loss and dielectric relaxation could be modelled ?

Title: Re: voltage dependent capacitor model
Post by Ken Kundert on Feb 18^th, 2008, 9:09pm

Well the point is that capacitors are charge conserving, so the path taken is irrelevant. So you just integrate the capacitance to get charge.

Concerning dielectric absorption, check out the paper in the Modeling section of this site.

-Ken

Title: Re: voltage dependent capacitor model
Post by Mihir Mudholkar on Aug 12^th, 2010, 1:06pm

Thanks a lot Ken for your valuable advice. I was also facing the same dilemma, however in MAST (Saber). The link you attached for your explaination of modeling non-linear capacitances is excellent.