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Design >> Mixed-Signal Design >> PLL - clock rate vs. loop BW
https://designers-guide.org/forum/YaBB.pl?num=1186520357

Message started by loose-electron on Aug 7^th, 2007, 1:59pm

Title: PLL - clock rate vs. loop BW
Post by loose-electron on Aug 7^th, 2007, 1:59pm

Hey all -

give me your take on this one ---

A generic ring oscillator PLL, if you look at the control systems equations, the input reference clock, and the loop BW have nothing to do with each other.

That said, most loops I have designed in the past have loop BW's that were less than the clock rate coming into PFD.

If you go to a higher loop BW than the reference clock frequency what issues arise and become problematic?

Lets say for sake of argument a reference clock of 1MHz and a loop BW of 10 MHz. The phase correction will be much less smooth, but if the zeta/damping is set properly it still should work fine, just look a lot more like a discrete corrections on the system rather than a linear response.

Any opinions or expereinces here to share?

thanks,
Jerry

Title: Re: PLL - clock rate vs. loop BW
Post by Visjnoe on Aug 7^th, 2007, 11:46pm

Dear Jerry,

loop BW and reference frequency in fact are related, or better yet: the reference frequency poses an upper limit
on the loop BW. A rule of thumb is that the loop BW should be smaller than 1/10th of the reference frequency.

I refer to the paper by Gardner on PLL stability. I don't know the exact details anymore, but the message is that if the loop BW is too high, the PLL can become unstable. You should be able to check this with a simple model (e.g. MATLAB). I personally have played around with such a model at one time and I indeed saw unstable behavior when I increased the loop BW uptil and beyond the reference frequency.

Regards

Peter

Title: Re: PLL - clock rate vs. loop BW
Post by vivkr on Aug 10^th, 2007, 1:07am

Hi Jerry,

I think what you are trying to ask has been asked by several others, and concerns the amount by which
the PLL bandwidth may be increased relative to the reference frequency without affecting the stability
too much.

A very good analysis is available in the paper "Analysis of Charge Pump PLLs" to be found on:

http://web.engr.oregonstate.edu/~hanumolu/publications/cas1_sep_04.pdf

This paper uses state-space analysis and a minimum of well-justified assumptions.

Regards
Vivek