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Design Languages >> Verilog-AMS >> global nodes
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Message started by morozmoroz on Aug 8^th, 2007, 3:57am

Title: global nodes
Post by morozmoroz on Aug 8^th, 2007, 3:57am

Hi, everyone!
As you probably know designers use in complex design global nodes (vdd!, gnd! etc.) - that means that block often doesn't have vdd, gnd pins. But when i create model for this block I would like to sense these nodes. So, question is - is any posibility to use global nodes in VerilogAMS? I use Cadence AMS Designer. The only way I know for now is to use parameters, but it is not very convenient.
Thanks is andvance!

Title: Re: global nodes
Post by boe on Aug 8^th, 2007, 4:14am

You can use Cadence hierarchical connections also with Verilog-AMS:
Declare them using the following
Code:

electrical (* integer inh_conn_prop_name="vss"; integer inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ;
electrical (* integer inh_conn_prop_name="vdd"; integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ;
...
analog Vsupply = V(\vdd! , \vss! )

NB: The escaped names end with a space!
BOE