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Design Languages >> Verilog-AMS >> why less time
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Message started by kamath on Aug 8^th, 2007, 4:56am

Title: why less time
Post by kamath on Aug 8^th, 2007, 4:56am

hai,
I tried a circuit by having some delay blocks designed and some compopnenets like oscillator,comparator etc in schematic but it took very long for simulation as compared to the same circuit in behavioural way modelled..Why?

I understand that the delay blocks might cause the problem.so if i replace the delay blocks of schematic into behavioural models then will time of simulation be reduced.