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Simulators >> Circuit Simulators >> long mixed mode simulation time in Spectre
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Message started by spanandiyer1979 on Aug 13^th, 2007, 8:27pm

Title: long mixed mode simulation time in Spectre
Post by spanandiyer1979 on Aug 13^th, 2007, 8:27pm

Hi

I am facing a problem of extremely long simulation times while running a Spectre simulation , consisting of a few differential nand gates ( meaning a few transistors) along with a block in VerilogA(just a delay element). If the blocks involving transistors are simulated separately or the verilogA block is simulated separately the simulation time is acceptable. However it seems to increase exhorbitantly when both of them are integrated together. The verilogA block just consists of a statement with keyword "analog" "begin" and "end". Also the waveforms involved have transition times of the order of 100ps...can anybody help ?

anand

Title: Re: long mixed mode simulation time in Spectre
Post by byang on Aug 13^th, 2007, 10:26pm

Hi, Anand,

If you can post your netlist, which seems simple, we'll try to simulate it and let you know the property of the simulation.

byang
www.gemini-da.com

Title: Re: long mixed mode simulation time in Spectre
Post by Visjnoe on Aug 14^th, 2007, 4:24am

Dear,

1. Are you experiencing convergence problems, maybe on the interface between transistor-level blocks and verilog-A modules? This might slow you down.

2. You have not introduced a $bound_step() statement in your verilog-A code, have you?

Regards

Peter

Title: Re: long mixed mode simulation time in Spectre
Post by spanandiyer1979 on Aug 14^th, 2007, 2:35pm

Hi

I think I might be facing convergence problem as you mentioned. However I am not sure how to solve it.
I have not used the bound_step() function. I am pasting the verilogA code below. the delays are all 50ps.

// VerilogA for pll_thesis, real_trans, veriloga

`include "constants.vams"
`include "disciplines.vams"
`include "../../pll_constants.h"

module real_trans(in , out);

input in ;
electrical in ;
output out ;
electrical out ;

parameter real tdelay = `VARIABLE_DELAY from [0:inf);
parameter real trise = `INV_RISE_TIME from (0:inf);
parameter real tfall = `INV_FALL_TIME from (0:inf);

real vout_val;
analog begin

vout_val = V(in) ;

V(out) <+ transition( vout_val, tdelay, trise, tfall);

end

endmodule

anand

Title: Re: long mixed mode simulation time in Spectre
Post by Visjnoe on Aug 14^th, 2007, 3:02pm

Dear,

if you have convergence issues/problems, you would be able to find out by checking the simulator's log file.
Please verify this before we continue.

regards

Peter

Title: Re: long mixed mode simulation time in Spectre
Post by spanandiyer1979 on Aug 14^th, 2007, 3:16pm

Hi

I dont see any problem in the log file except that it shows the step is too small...i am pasting part of the log for your perusal...it would be very helpful if you help...

thanks
anand

....

Circuit inventory:
nodes 83
equations 417
ahdl simulator 1
bsim4 162
isource 1
quantity 9
real_trans 1
vsource 9

Entering remote command mode using MPSC service (spectre, ipi, v0.0,
spectre8_22533_37, ).

************************************************
Transient Analysis `tran': time = (0 s -> 50 ns)
************************************************
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 50 ns
step = 100 ps
maxstep = 200 ps
ic = all
skipdc = no
reltol = 1e-03
abstol(I) = 1 pA
abstol(V) = 1 uV
temp = 27 C
tnom = 25 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS
maxrsd = 0 Ohm
mos_method = s
mos_vres = 50 mV

tran: time = 1.25 ns (2.5 %), step = 1.688 ps (3.38 m%)
tran: time = 1.601 ns (3.2 %), step = 23.55 fs (47.1 u%)
tran: time = 1.813 ns (3.63 %), step = 330 fs (660 u%)
tran: time = 2.052 ns (4.1 %), step = 8.183 fs (16.4 u%)
tran: time = 2.064 ns (4.13 %), step = 2.563 fs (5.13 u%)
tran: time = 2.079 ns (4.16 %), step = 4.587 fs (9.17 u%)
tran: time = 2.096 ns (4.19 %), step = 1.427 fs (2.85 u%)
tran: time = 2.102 ns (4.2 %), step = 1.164 fs (2.33 u%)
tran: time = 2.11 ns (4.22 %), step = 5.186 fs (10.4 u%)
tran: time = 2.119 ns (4.24 %), step = 29.82 fs (59.6 u%)
tran: time = 2.143 ns (4.29 %), step = 14.98 fs (30 u%)
tran: time = 2.195 ns (4.39 %), step = 12.51 fs (25 u%)
tran: time = 2.322 ns (4.64 %), step = 23.56 fs (47.1 u%)
tran: time = 2.442 ns (4.88 %), step = 35.76 fs (71.5 u%)
tran: time = 2.503 ns (5.01 %), step = 92.79 fs (186 u%)
tran: time = 2.53 ns (5.06 %), step = 2.152 fs (4.3 u%)
tran: time = 2.541 ns (5.08 %), step = 8.327 fs (16.7 u%)
tran: time = 2.551 ns (5.1 %), step = 1.427 fs (2.85 u%)
tran: time = 2.553 ns (5.11 %), step = 297.5 as (595 n%)
tran: time = 2.557 ns (5.11 %), step = 771.8 as (1.54 u%)
tran: time = 2.559 ns (5.12 %), step = 647 as (1.29 u%)
tran: time = 2.561 ns (5.12 %), step = 359.8 as (720 n%)
tran: time = 2.563 ns (5.13 %), step = 345.9 as (692 n%)
tran: time = 2.564 ns (5.13 %), step = 181.8 as (364 n%)
tran: time = 2.566 ns (5.13 %), step = 3.053 fs (6.11 u%)
tran: time = 2.569 ns (5.14 %), step = 957 as (1.91 u%)
tran: time = 2.572 ns (5.14 %), step = 2.023 fs (4.05 u%)
tran: time = 2.575 ns (5.15 %), step = 785 as (1.57 u%)
tran: time = 2.578 ns (5.16 %), step = 9.419 fs (18.8 u%)

..............

Title: Re: long mixed mode simulation time in Spectre
Post by byang on Aug 14^th, 2007, 9:42pm

There might be convergence problem. The time steps are getting too small sometimes:
tran: time = 2.563 ns (5.13 %), step = 345.9 as (692 n%)
tran: time = 2.564 ns (5.13 %), step = 181.8 as (364 n%)

You can try option method=gear2. This might be caused by trap ringing.

byang
www.gemini-da.com

Title: Re: long mixed mode simulation time in Spectre
Post by spanandiyer1979 on Aug 14^th, 2007, 10:46pm

Hi

Thanks for the reply. I added the following statement after the "analog begin" statement : @(timer(0,50p)).

The code looks like this:

// VerilogA for pll_thesis, real_trans, veriloga

`include "constants.vams"
`include "disciplines.vams"
`include "../../pll_constants.h"

module real_trans(in , out);

input in ;
electrical in ;
output out ;
electrical out ;

parameter real tdelay = `VARIABLE_DELAY from [0:inf);
parameter real trise = `INV_RISE_TIME from (0:inf);
parameter real tfall = `INV_FALL_TIME from (0:inf);

real vout_val;
analog begin
@(timer(0,50p))
vout_val = V(in) ;

V(out) <+ transition( vout_val, tdelay, trise, tfall);

end

endmodule

This seems to make the simulations run at normal rates.

The input to the module comes from circuit having some transistors and the output goes to a circuit with a bunch of transistors.....but am not sure whether adding the "timer" line will lead to proper results...

anand