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Design >> RF Design >> isolation
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Message started by aaron_do on Aug 13^th, 2007, 11:29pm

Title: isolation
Post by aaron_do on Aug 13^th, 2007, 11:29pm

Hi all,

just wondering, I'm using a n-well process, so does that mean my pmos will have better immunity to substrate noise than nmos? Basically, there's a diode between the nwell and the psubstrate and so the psubstrate would have to be above VDD to leak...

thanks,
Aaron

Title: Re: isolation
Post by vivkr on Aug 13^th, 2007, 11:51pm

Hi Aaron,

Normally, the additional diode will help you in getting better immunity, provided your VDD (tied to the well) does not get contaminated by noise.
This seems like the standard CMOS process though. Or am I missing something?

Regards
Vivek

Title: Re: isolation
Post by aaron_do on Aug 14^th, 2007, 2:00am

Hi Vivek,

thanks for the reply. In the process i'm using, the nmos have no wells. They are directly in the p-substrate. So i was thinking that they would suffer more substrate noise than the pmos in the nwells.

cheers,
Aaron

Title: Re: isolation
Post by vivarf on Sep 3^rd, 2007, 7:13pm

I think it is trivial that nmos will suffer more substrate noise since its channel is inside the whole substrate instead of seperated well as p-well process.