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Design Languages >> Verilog-AMS >> oscillator
https://designers-guide.org/forum/YaBB.pl?num=1187263634

Message started by kamath on Aug 16^th, 2007, 4:27am

Title: oscillator
Post by kamath on Aug 16^th, 2007, 4:27am

i am designing period-controlled-oscillator,but not getting the desired output from block.please suggest any changes to be made

module myosc(in,out,clk);
input in,clk;
output out;
electrical in,out,clk;

parameter real vh=1.5;
parameter real vl=0;

parameter real vtrans=0.6;
parameter real maxp=(1/5000000);
parameter real minp=(1/500);
integer comp;
integer n;
real period;
real step;

analog begin

@(initial_step)begin
period=(1/500000);

step=(1/5000) + $abstime;
end

@(timer(step))begin
n=!n;
step=step+(0.5*period);
end

@(cross(V(clk)-vtrans,1))
begin
if((V(in)-vtrans)>0)
comp=1;
else
comp=-1;
period = period +(comp*step);
end

if(period>maxp)
period=maxp;
if(period<minp)
period=minp;

V(out)<+transition(n?vh:vl,0,100p);
end

endmodule

Title: Re: oscillator
Post by Geoffrey_Coram on Aug 16^th, 2007, 8:05am

kamath wrote on Aug 16^th, 2007, 4:27am:

@(initial_step)begin
period=(1/500000);

step=(1/5000) + $abstime;
end

1) Why $abstime? Won't it always be 0 when initial_step occurs?

2) the step is much larger than the period (step = 200u, period = 2u), so the timer(step) will let 100 periods elapse ...